Gate Drive Optocoupler Basic Design for IGBT / MOSFET Applicable to All Gate Drive Optocouplers
Application Note 5336
Introduction
This application note covers the topic of calculating gate driver power and thermal dissipation of the gate drive optocoupler IC. Gate drive optocouplers are ud to drive, turning-on and off, power miconductor switches, MOSFETs / IGBTs. The gate drive power calculation can be divided into three parts; power consumed or lost in the internal circuitry of the driver, power nt to the power miconductor switches (IGBT/MOSFET) and power lost at the external component between the driver IC and the power miconductor switch, e.g. across external gate resistor. In the following example, we will discuss a IGBT gate driver design using Avago ACPL-332J (2.5Apeak in-telligent gate driver) This design guide is applicable for MOSFET gate driver.IGBT/MOSSFET Gate Resistor
When choosing the value of R G, it is important to look from the point from both gate driver IC and the power miconductor switches, MOSFET / IGBT. For the gate driver IC, we choo an R G that is within the IC maximum allowable power disippation rating while sourcing/ sinking the highest possible driver current. From the IGBT or MOSFET point of view, the gate resistor influences the voltage chang
e dV CE/dt and current change di C/dt during the turn on and turn off period.
So it is important when a designer choos an IGBT or MOSFET, the appropriate gate driver optocoupler is also chon as the current and power rating of this driver determine how fast the IGBT or MOSFET is turn-on and turn-off.
Figure 1. Block Diagram of ACPL-332J
Figure 2. V OL vs I OL
Step I: Calculate R G minimum from I OL peak specification:
To find the peak charging l OL assume that the gate is initially charged the steady-state value V CC . For ACPL-332J, the voltage drop is linearly approximated as 4.5V for 2.5A output at 70°C (Fig 2: V OL vs I OL ). Therefore apply the following relationship:
0123456780
0.5
1
1.5
2
2.5
恨的英语
I oL -OUTPUT LOW CURRENT -A
V O L -L O W O U T P U T V O L T A G E D R O P -
V
Gate Drive Power Operation within IC Maximum Allowable Power Ratings
The power dissipation of the gate drive optocoupler is a combination of output-side power to IGBT/MOSFET, red circle and the input-side power due to input LED power dissipation, blue circle. The power dissipation for cond LED ud in fault feedback is neglected as the current to drive the open-collector transistor is small. The calculation steps are:
1. Calculate the minimum desired R G according to the maximum peak gate current
2. Calculate total power dissipation
3. Compare the input and output power dissipation calculated in step #2 to the maximum recommended dissipation for the IC. (If the maximum recommended level has been exceeded, it may be necessary to rai the value of R G to lower the switching power and repeat step #2.)In this example, the total input and output power dissipa-tion of ACPL-332J is calculated given the following condi-tions:
有钱的成语• I G = I ON, MAX ~ 2.0 A • V CC2 = 18 V
• V EE = -5 V, (Note: V EE = 0V if negative voltage supply is not required in application)• f SWITCH = 15 kHz
• Ambient Temperature = 70°C
I OL,PEAK = 2.0A @ 4.5V internal voltage drop R g = V CC2 – V EE – V OL = (18V - (-5V) - 6.3)/ 2.5 A = 6.68 Ω (approximately 6.8 Ω)
Note: The value of the gate resistance has a significant impact on the dynamic performance of IGBTs/MOSFETs. A smaller gate resistor charges and discharges the power transistor input capacit
ance faster reducing switching times and switching loss. The trade off is that this could lead to higher voltage oscillations. In the MOSFET and IGBT datasheet, there is usually a recommended gate resistor which is ud for the datasheet characterization. However, designer should be cautious not to over-drive the gate drive IC using the recommended gate resistance from the IGBT or MOSFET datasheet.
Step II: Calculate total power dissipation in the gate driver:
The total power dissipation (P T ) is equal to the sum of the input-side power (P I ) and output-side power (P O ) dissipa-tion:P T = P I + P O
P I = I F(ON) ,max * V F,max where,
I F(ON),max = 12mA V F,max = 1.95V
The I F(ON) can be found in the recommended operting conditions and V F can be found in ACPL-332J datasheet, Table 5 of the electrical specifications.Electrical Specification
Min
Typ Max Units Input Forward Voltage, V F 1.
1.6
1.95
V
P O = P O(BIAS) + P O(SWTICH)
= I CC2.MAX * (V CC2–V EE ) + ∆V GE * Q G * f SWITCH where,
P O(BIAS) = steady-state power in the driver due to
biasing the device. P O(SWITCH) = Driver power for charging and
discharging of device gate capacitances. I CC2.MAX = Supply Current to power internal circuity ∆V GE = V CC2 + |V EE |
Q G
= Total gate charge of the IGBT or MOSFET as described in the manufacturer specification (Illustrated in Figure 3) = 240nC (approximation for a 100A IGBT)
f SWITCH = switchin
g frequency of application
The output detector junction temperature is given by T J = P D *( q J-P + q P-A ) + T A
发烧怎么处理
Using the q J-P = q 9-12 = 30°C/W (ACPL-332J Table 7. Package Characteristic) and T A of 70°C and assuming the thermal resistance from pin to ambient, q P-A is 50°C/W T J = 197.8*(30+50) + 70°C = 85.8°C
If the juntion temperature is higher than the maximum junction temperature rating (in this ca 125°C), the desired specification must be derated according.Designers should note that the thermal resistance between pin to ambient is also the PCB heatsink thermal resistance. This thermal resistance is then dependent on the area size on the PCB and the free air-flow.
Further Topics:
Higher Output Current Using an External Current Buffer:
To increa the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer s
hown in Figure 75 of HCPL-316J data sheet) may be ud. Inverting types are not compatible with the desatura-tion fault protection circuitry and should be avoided. To prerve the slow IGBT turn-off feature during a fault condition, a 10 nF capacitor should be connected from the buffer input to V EE and a 10Ω resistor inrted between the output and the common npn/ pnp ba. The MJD44H11/ MJD45H11 pair is appropriate for currents up to 8A maximum. The D44VH10/ D45VH10 pair is appro-priate for currents up to 15 A maximum.
孕妇如何控制血糖
Thermal Model
Most of the steady state thermal model of gate drive op-tocouplers can be found in AN1087. The thermal resis-tance values given in this model can be ud to calculate the temperatures at each node for a given operating condition.
Figure 3. Typical IGBT Gate Charge Curve
V GE (V)
(C)
记叙文素材
G
Step III: Compare the calculated power dissipation with the absolute maximum values in the IC:现场6s管理
For the ACPL-332J, the maximum power dissipation can be found in Table 3 of the ACPL-332J data sheet. Absolute Maximum rating in AV02-0120EN data sheet. Also, it requires derating of 10mW/°C if the operating tempera-ture is above 90°C (Note. 2 ACPL-332J datasheet).Absolute Maximum Rating
Min
Max Units Output IC Power Dissipataion, Po 600mW
Input IC Power Dissipation, P I
150P I = 23.4 mW < 150 mW (abs. max.) )
OK
P O = 197.8 mW < 600 mW (abs. max.) ) OK
Therefore, the power dissipation absolute maximum rating has not been exceeded for the above example.
Note: Heat dissipation for different packages require derating when the operating temperature exceed a certain level. For ACPL-332J, as operating temperature is below 90oC, derating is not necessary. Operating temperature is different for different products
Another method to check if the device is within the maximum limits is to calculate the junction temperature of the device. We continue to u the example provided earlier.
Power dissipation, P D = 23.4 + 197.8 = 221.2mW
Using the above information, we calculate both P I and P O below
P I = 12 mA * 1.95 V = 23.4mW P O = P O(BIAS) + P O(SWITCH)
= 5.0 mA * (18 V – (–5 V)) + (18V + 5V) * 240nC * 15 kHz = 115mW + 82.8mW = 197.8 mW
观赏的反义词Printed Circuit Board Layout Considerations
Adequate spacing should always be maintained between the high voltage isolated circuitry and any i
nput refer-enced circuitry. Care must be taken to provide the same minimum spacing between two adjacent high-side isolated regions of the printed circuit board. Insufficient spacing will reduce the effective isolation and increa parasitic coupling that will degrade CMR performance. The placement and routing of supply bypass capacitors requires special attention. During switching transients, the majority of the gate charge is supplied by the bypass capacitors. Maintaining short bypass capacitor trace lengths will ensure low supply ripple and clean switching waveforms.
Figure 5 below shows example PCB layout using HCPL-316J gate driver optocoupler. Ground Plane connections are necessary for pin 4 (GND1) and pins 9 and 10 (V EE) in order to achieve maximum power dissipation as the HCPL-316J is designed to dissipate the majority of heat generated through the pins. This is also applicable for ACPL-332J. For this ca, the ground plane connections are pin 1, pin 4 (V SS) and pin 4 (V SS), pin 9 and 12 (V EE). Actual power dissipation will depend on the application environment (PCB layout, air flow, part placement, etc.) See Application Note 1087 ction for details on how to estimate junction temperature.
The layout examples in Figure 5 have good supply bypassing and thermal properties, exhibit small PCB foot-prints, and have easily connected signal and supply lines. The four examples cover single sided and double sided component placement, as well as minimal and improved performance circuit
s.
Figure 5. Recommended layout(s)滇黄精
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AV0 -04 1EN - July 9, 008
