1
Features
•Full duplex transmission over a single twisted pair •Selectable 80 or 160 kbit/s line rate •Adaptive echo cancellation •Up to 3km (9171) and 4 km (9172)•ISDN compatible (2B+D) data format •Transparent modem capability
•Frame synchronization and clock extraction •Zarlink ST-BUS compatible
团学干部•
Low power (typically 50mW), single 5V supply
Applications
•Digital subscriber lines
•High speed data transmission over twisted wires •Digital PABX line cards and telephone ts •
80 or 160kbit/s single chip modem
Description
The MT9171 (DSIC) and MT9172 (DNIC) are pin for pin compatible replacements for the MT8971 and MT8972, respectively. They are multi-function devices capable of providing high speed, full duplex digital transmission up to 160kbit/s over a twisted wire pair.They u adaptive echo-cancelling techniques and transfer data in (2B+D) format compatible to the ISDN basic rate. Several modes of operation allow an easy interface to digital telecommunication networks including u as a high speed limited distance modem
March 2006
Ordering Information
MT9171/72AE 22 Pin PDIP Tubes MT9171/72AN 24 Pin SSOP Tubes MT9171/72AP 28 Pin PLCC Tubes
MT9171/72APR 28 Pin PLCC Tape & Reel MT9171/72ANR 24 Pin SSOP Tape & Reel MT9171/72AE122 Pin PDIP*Tubes MT9171/72AP128 Pin PLCC*Tubes MT9171/72AN124 Pin SSOP*Tubes
MT9171/72APR128 Pin PLCC*Tape & Reel MT9171/72ANR124 Pin SSOP*
Tape & Reel
*Pb Free Matte Tin
-40°C to +85°C
ISO 2-CMOS ST-BUS FAMILY MT9171/72
Digital Subscriber Interface Circuit Digital Network Interface Circuit
Data Sheet
Figure 1 - Functional Block Diagram证人出庭申请书
DSTi/Di CDSTi/
F0/CLD C4/TCK F0o/RCK
MS0MS1MS2RegC
DSTo/Do CDSTo/
CDo
Transmit Interface
Prescrambler Scrambler
Control Register Transmit/Clock Receive Timing &Control Status
Transmit Timing Master Clock Pha Locked
Sync Detect Receive
DPLL
Receive Interface
De -Prescrambler
Descrambler
Differentially Encoded Bipha
Receiver
Differentially Encoded Bipha Transmitter Transmit Filter &Line Driver
Receive Filter
-1+2
MUX
笔记本键盘膜Address
Echo Canceller Error Signal Echo Estimate
V Bias
V DD V SS V Bias V Ref
L OUT
L OUT
DIS
Precan
L IN
OSC2
OSC1
—
+
∑
CDi
MT9171/72
Data Sheet
with data rates up to 160kbit/s. Both devices function identically but with the DSIC having a shorter maximum loop reach specification. The generic "DNIC" will be ud to reference both devices unless otherwi noted.The MT9171/72 is fabricated in Zarlink’s ISO 2-CMOS process.
Figure 2 - Pin Connections
Pin Description
Pin # Name Description
222428112L OUT Line Out. Transmit Signal output (Analog). Referenced to V Bias .
223V Bias Internal Bias Voltage output. Connect via 0.33µF decoupling capacitor to V DD .3
3
4V Ref
Internal Reference Voltage output. Connect via 0.33µF decoupling capacitor to V DD .
4,5,64,5,65,7,8MS2-MS0Mode Select inputs (Digital). The logic levels prent on the pins lect the
various operating modes for a particular application. See Table 1 for the operating modes.779RegC Regulator Control output (Digital). A 512kHz clock ud for switch mode power supplies. Unud in MAS/MOD mode and should be left open circuit.
tanα8
9
10
F0/CLD
Frame Pul/C-Channel Load (Digital). In DN mode a 244ns wide negative pul input for the MASTER indicating the start of the active channel times of the device. Output for the SLAVE indicating the start of the active channel times of the device. Output in MOD mode providing a pul indicating the start of the C-channel.
1234567891011
12
1314222120191817161522 PIN PDIP
LOUT VBias VRef MS2MS1MS0RegC F0/CLD CDSTi/CDi CDSTo/CDo
VSS VDD LIN TEST
LOUT DIS Precan OSC1OSC2C4/TCK F0o/RCK DSTi/Di DSTo/Do
28 PIN PLCC
2743212826
56789101125242322212019
17121314151618
•
L O U T V B i a s V R e f N C V D D L I N T E S T
NC
LOUT DIS Precan OSC1OSC2NC C4/TCK
MS2NC MS1MS0RegC F0/CLD
NC
C D S T i /C D i C D S T o /C D o V S S D S T o /D o N C F 0o /R C K D S T i /D i 12345678910111213
141516242322212019181724 PIN SSOP
LOUT VBias VRef MS2MS1MS0RegC F0/CLD CDSTi/CDi CDSTo/CDo
VSS
NC VDD LIN TEST
LOUT DIS Precan OSC1OSC2C4/TCK F0o/RCK DSTi/Di DSTo/Do
NC 零售经营
MT9171/72
Data Sheet
9
10
12
CDSTi/CDi Control/Data ST-BUS In/Control/Data In (Digital). A 2.048Mbit/s rial control & signalling input in DN mode. In MOD mode this is a continuous bit stream at the bit rate lected.
101113
CDSTo/CDo Control/Data ST-BUS Out/Control/Data Out (Digital). A 2.048Mbit/s rial control & signalling output in DN mode. In MOD mode this is a continuous bit stream at the bit rate lected.111214V SS
Negative Power Supply (0V).
121315DSTo/Do Data ST-BUS Out/Data Out (Digital). A 2.048Mbit/s rial PCM/data output in
DN mode. In MOD mode this is a continuous bit stream at the bit rate lected.131416DSTi/Di
Data ST-BUS In/Data In (Digital). A 2.048Mbit/s rial PCM/data input in DN mode. In MOD mode this is a continuous bit stream at the bit rate lected.
14
15
17
蟹黄豆腐羹F0o/RCK Frame Pul Out/Receive Bit Rate Clock output (Digital). In DN mode a 244ns
wide negative pul indicating the end of the active channel times of the device to allow daisy chaining. In MOD mode provides the receive bit rate clock to the system.151619
C4/TCK
Data Clock/Transmit Baud Rate Clock (Digital). A 4.096MHz TTL compatible clock input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin provides the transmit bit rate clock to the system.
161721OSC2Oscillator Output . CMOS Output.171922OSC1
Oscillator Input . CMOS Input. D.C. couple signals to this pin. Refer to D.C. Electrical Characteristics for OSC1 input requirements.
18
20
23
Precan
Precanceller Disable. When held to Logic ’1’, the internal path from L OUT to the precanceller is forced to V Bias thus bypassing the precanceller ction. When logic ’0’, the L OUT to the precanceller path is enabled and functions normally. An internal pulldown (50k Ω) is provided on this pin.8,18
1,6,11,18,20,25NC
No Connection. Leave open circuit
1921
24
L OUT DIS L OUT Disable. When held to logic “1”, L OUT is disabled (i.e., output = V Bias ). When
logic “0”, L OUT functions normally. An internal pulldown (50k Ω) is provided on this pin.202226TEST Test Pin. Connect to V SS .212327L IN Receive Signal input (Analog). 22
24
28
V DD
Positive Power Supply (+5V) input.三年级日记三百字
Pin Description (continued)
Pin # Name Description
MT9171/72Data Sheet
Figure 3 - DV Port - 80kbit/s (Modes 2, 3, 6)
Figure 4 - DV Port - 160kbit/s (Modes 2, 3, 6)
MT9171/72Data Sheet Functional Description
The MT9171/72 is a device which may be ud in practically any application that requires high speed data transmission over two wires, including smart telephone ts, workstations, data terminals and computers. The device supports the 2B+D channel format (two 64kbit/s B-channels and one 16kbit/s D-channel) over two wires as recommended by the CCITT. The line data is converted to and from the ST-BUS format on the system side of the network to allow for easy interfacing with other components such as the S-interface device in an NT1 arrangement, or to digital PABX components.
Smart telephone ts with data and voice capability can be easily implemented using the MT9171/72 as a line interface. The device’s high bandwidth and long loop length capability allows its u in a wide variety of ts. This can be extended to provide full data and voice capability to the private subscriber by the installation of equipment in both the home and central office or remote concentration equipment. Within the subscriber equipment the MT9171/72 would terminate the line and encode/ decode the data and voice for transmission while additional electronics could provide interfaces for a standard telephone t and any number of data ports supporting standard data rates for such things as computer communications and telemetry for remote meter reading. Digital workstations with a high degree of networking capability can be designed using the DNIC for the line interface, offering up to 160 kbit/s data transmission over existing telephone lines. The MT9171/72 c
ould also be valuable within existing computer networks for connecting a large number of terminals to a computer or for intercomputer links. With the DNIC, this can be accomplished at up to 160kbit/s at a very low cost per line for terminal to computer links and in many cas this bandwidth would be sufficient for computer to computer links.
Figure 1 shows the block diagram of the MT9171/72. The DNIC provides a bidirectional interface between the DV (data/voice) port and a full duplex line operating at 80 or 160kbit/s over a single pair of twisted wires. The DNIC has three rial ports. The DV port (DSTi/Di, DSTo/Do), the CD (control/data) port (CDSTi/CDi, CDSTo/CDo) and a line port (L IN, L OUT). The data on the line is made up of information from the DV and CD ports. The DNIC must combine
information received from both the DV and CD ports and put it onto the line. At the same time, the data received from the line must be split into the various channels and directed to the proper ports. The usable data rates are 72 and144kbit/s as required for the basic rate interface in ISDN. Full duplex transmission is made possible through on board adaptive echo cancellation.
The DNIC has various modes of operation which are lected through the mode lect pins MS0-2. The two major modes of operation are the MODEM (MOD) and DIGITAL NETWORK (DN) modes. M
OD mode is a transparent 80 or 160kbit/s modem. In DN mode the line carries the B and D channels formatted for the ISDN at either 80 or 160 kbit/s. In the DN mode the DV and CD ports are standard ST-BUS and in MOD mode they are transparent rial data streams at 80 or 160kbit/s. Other modes include: MASTER (MAS) or SLAVE (SLV) mode, where the timeba and frame synchronization are provided externally or are extracted from the line and DUAL or SINGLE (SINGL) port modes, where both the DV and CD ports are active or where the CD port is inactive and all information is pasd through the DV port. For a detailed description of the modes e “Operating Modes” ction.
In DIGITAL NETWORK (DN) mode there are three channels transferred by the DV and CD ports. They are the B, C and D channels. The B1 and B2 channels each have a bandwidth of 64kbit/s and are ud for carrying PCM encoded voice or data. The channels are always transmitted and received through the DV port (Figures 3, 4, 5, 6). The C-channel, having a bandwidth of 64kbit/s, provides a means for the system to control the DNIC and for the DNIC to pass status information back to the system. The C-channel has a Houkeeping (HK) bit which is the only bit of the C-channel transmitted and received on the line. The 2B+D channel bits and the HK bit are double-buffered. The D-channel can be transmitted or received on the line with either an 8, 16 or 64kbit/s ba
ndwidth depending on the DNIC’s mode of operation. Both the HK bit and the D-channel can be ud for end-to-end signalling or low speed data transfer. In DUAL port mode the C and D channels are accesd via the CD port (Figure 7) while in SINGL port mode they are transferred through the DV port (Figures 5, 6) along with the B1 and B2 channels.
MT9171/72Data Sheet
Figure 5 - DV Port - 80kbit/s (Modes 0,4)
Figure 6 - DV Port - 160kbit/s (Modes 0,4)
In DIGITAL NETWORK (DN) mode, upon entering the DNIC from the DV and CD ports, the B-channel data, D-channel D0 (and D1 for 160kbit/s), the HK bit of the C-channel (160kbit/s only) and a SYNC bit are combined in a rial format to be nt out on the line by the Transmit Interface (Figures 11, 12). The SYNC bit produces an alternating 1-0 pattern each frame in order for the remote end to extract the frame alignment from the line. It is possible for the remote end to lock on to a data bit pattern which simulates this alternating 1-0 pattern that is not the true SYNC. To decrea the probability of this happening the DNIC may be programmed to put the data through a prescrambl
er that scrambles the data according to a predetermined polynomial with respect to the SYNC bit. This greatly decreas the probability that the SYNC pattern can be reproduced by any data on the line. In order for the echo canceller to function correctly, a dedicated scrambler is ud with a scrambling algorithm which is different for the SLV and MAS modes. The algorithms are calculated in such a way as to provide orthogonality between the near and far end data streams such that the correlation between the two signals is very low.
班主任基本功For any two DNICs on a link, one must be in SLV mode with the other in MAS mode. The scrambled data is differentially encoded which rves to make the data on the line polarity-independent. It is then bipha encoded as shown in Figure 10. See “Line Interface” ction for more details on the encoding. Before leaving the DNIC the differentially encoded bipha data is pasd through a pul-shaping bandpass transmit filter that filters out the high and low frequency components and conditions the signal for transmission on the line.
