The initial capacitance value that is chon for a bypass capacitor is done to provide a
minimum current need. When a clock buffer’s outputs switch, the power terminals will sag
due to the die to PCB voltage drop. This drop, or droop as it refers to a temporary
condition, occurs becau of the inductance and resistance of the device lead frame and
bonding wire. The bypass capacitor function is to supply this momentary need in current
with its stored charge. To do this, it must store a minimum amount of energy. The buffer
loading determines this energy value and the amount stored is given by the formula:
Q = CV
Where : Q = Charge
V = applied voltage
C = capacitance in farads
Differentiating this equation yields:
I(t) = dQ/dt = C * dV/dt
C = I dt/dV
This equation allows us to calculate the capacitance required to prevent voltage droop due
to the switching clock outputs. For example, suppo we have a 3.3V clock buffer with
eight outputs driving a 50-ohm trace with a ri/fall time of 2 ns. Let’s also assume that a
droop of 50 mV is the maximum amount of voltage droop allowable to the component.
First we need to calculate the output current during the ri of the clocks. Assuming the
outputs reach 3V, each output requires 3/50 ohm = 60 mA. Becau the buffer has eight
outputs, it requires a total of 480 mA.
Solving for C yields:
C = ( 480 mA * 2 ns )/50 mV
C = 0.0192 µF
This suggests that this amount of total capacitance is required on the component to永远近义词
maintain less than 50 mV of droop. Often, 0.1 µF capacitors are ud for bypassing.
Another way to view this situation is that a 0.1 µF capacitor supplies 480 mA of
instantaneous current in 2 ns with only 9.6 mV of voltage droop across the capacitor.
This example assumed a worst-ca voltage swing on the outputs of 3 volts. Depending on
the termination method ud, this swing could be less than this amount. However, since
this is ud only as a guide, its best to over estimate the value.
Capacitor Filtering
Similar to the filters discusd earlier in the chapter, decoupling capacitors block unwanted
浪漫的表白情书AC variations (noi) in two directions. They prevent noi from entering the device from
the power plane and they also suppress noi from the device to the power plane.
Decoupling caps are more than a capacitor. They are in effect a capacitor in ries with an
inductor and a resistor as shown in Figure 5.20.
Figure 5.20 Capacitor Model
This is important in understanding what happens during the operation of a capacitor.
Becau it is filtering AC signals, the characteristics of the capacitor are always changing.
To understand the operation over frequency, curves are provided for each value, package
type, and composition. Figure 5.21 shows the impedance versus frequency curve for a
0.1 µF capacitor packaged in a 0603 body.
The curve shows this capacitor resonates at approximately 11 MHz which is the point
where the impedance is lowest. On either side of this frequency, the amount of impedance
increas. The ideal capacitor has zero ohms at tho frequencies that need bypassing.
The 0.1 µF capacitor has been ud for decoupling for many years. Even when clock rates
were as slow as 100 kHz, the 0.1 µF was ud. As the clock frequencies incread, it was
thought the decoupling capacitor needed to decrea in value in order to address the鸡爪煲汤
higher frequencies. Many designs started to u 0.01 µF capacitors instead of the 0.1 µF.
Figure 5.22 shows a 0.01 µF capacitor curve in the same 0603 package as the 0.1 µF.
原版翻译如下：
用作旁路电容器的起初确定的电容值要能提供所需要最小的电流。当一个时钟缓冲器的输出切换时，由于PCB 电压降减小，电源接线端的压降也下降。这种下降，或者说瞬间的下降是由于器件的引线框(或焊接框架)和焊线引起的。旁通电容的作用就是用其存储的电荷去补充这瞬间的电流需要。为此，电容必须存储最低的能量值。缓冲器负载决定了存储能量，并由公式中国闭关锁国Q=CV确定存储的量，其中Q简爱名言名句是电量，V是施加的电压，C是用法拉表示的电容值。
对公式求微分，得到有
I(t) = dQ/dt = C* dV/dt
彩虹的微笑歌曲C=Idt/dV
这个公式让我们可以计算防止时钟输出切换时引起的电压下降需要的电容大小。如用一个带8个输出的3.3V时钟缓冲器去驱动一个50Ω线路，上升/下降时间为2ns，假定元件允许的最大电压降为50mV。首先计算出时钟上升段时的输出电流，假定达到3V，则每个输出需要3V/50Ω身躯造句=60mA电流，共有8个输出，总共480mA。由公式计算出C= (480mA*2ns)/50mV
C=0.0192uF
表明元件需要这么大的总电容来维持小于50mV压降。通常，用0.1uF电容做旁通。另外一种看待方法是0.1uF电容能提供2ns内480mA瞬间电流并且电容两边只有9.6mV压降。这个例子列出了3V输出电压情况下最坏的电压摆动情况。摆动值与端接的形式有关，可能小于这个值。由于只用作指导性，最好估大些这个值。
相似于本章前面讨论的，去耦电容能阻止两个方向上多余的交流(AC)变化(噪声)。防止噪声从电源平面进入器件，也防止噪声从器件进入电源平面。
去耦电容不仅仅是一个电容器，它的效果相当于一个电容器和一个电感、电阻串联在一起。图5.20示。
这个图对理解电容器工作时发生了什么非常重要。由于它过滤交流信号，电容器的特性总是在变化的。为理解频率作用，为每个值、封装类型、组成成分的电容规定了曲线。图5.21是0603封装的0.1uF电容器的频率与阻抗的曲线。曲线显示电容器在近似11MHz处共振，此处正是阻抗最低点。这一点两侧，阻抗在增大。理想的电容器在需要旁通的频率点阻抗为0。
0.1uF孕妇可以吃桃胶吗电容器用于去耦已经很多年了，即使时钟速率降到100KHz，0.1uF电容也在用。随
着时钟速率增加，需要考虑减小去耦电容数值来对付更高频率的。许多设计者们开始使用0.01uF代替0.1uF电容。图5.22是一条与0.1uF电容相同0603封装的0.01uF电容器曲线。
尽管器件的共振频率稍微增大，但更高频率处的阻抗没有变化。除了接近共振点的较窄的频率带内，0.01uF电容器并没有实质性的优点。
但是为什么较小的电容在更高的频率没有能提供较低的阻抗呢？答案是电感。伴随封装产生的相当大数值的电感是更高频时的限制因素。电感受引脚的金属材料尺寸影响。为了减小电感，封装的尺寸需要减小。这不仅对0.01μF电容起作用，还有利于0.1μF电容。
