AN1266
APPLICATION NOTE Benchmarking Flash NOR and Flash NAND memories
for Code and Data Storage
CONTENTS
s INTRODUCTION
s CELL STRUCTURE s CELL DIMENSIONS s MULTI LEVEL CELLS s OPERATIONAL我的理想300字
DIFFERENCES
s COST TRENDS
s CONCLUSION
s REFERENCES INTRODUCTIOM
When choosing a Flash memory for a particular application it is important to know which type of Flash
Memory is most suitable. There are now many manufacturers offering a wide range of Flash Memories and urs can be daunted by the prospect of lecting the correct product for their application.
This document aims to give a background on the underlying technologies associated with Flash Memories. It will give the reader a clearer picture of which type of Flash Memory to choo for their application. The advantages and disadvantag-es of each type of memory is discusd along with the under-lying principles that govern the properties of the memory. There are two fundamental Array Architecture that distinguish the type of the Flash Memory, NOR and NAND. Although both the types of memories can store large amounts of data, only the NOR type is suitable for fast random access required for ex-ecuting code directly from the Flash Memory, saving on shad-ow RAM costs.
CELL STRUCTURE
The Basic Cell in a Flash Memory is a single MOS transistor built with a Floating Gate between the control gate and the p-substrate. Figure 1 shows a typical cross ction of the transis-tor.
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The Floating Gate stores charge (electrons); the amount of charge on the gate determines whether the Flash Memory cell holds a value of ‘1’ or ‘0’. (In Multi-Bit Cells more than one bit can be stored, this is discusd later). To read the contents of the cell a voltage is placed across CS; the current through DS depends on the charge stored in the Floating Gate. By measuring I DS the charge in the
Floating Gate is found.
There are various methods of laying out all of the Floating Gate transistors and connecting C, D and S in a Flash Memory array. Figure 2 shows the connection technique for NOR and NAND Flash Memories.
In the NOR architecture a read is performed by connecting the Source Line to ground, raising the vol
tage level on the Word Line to the n voltage and connecting the Bit Line to the n amplifier. If the ad-dresd cell is programmed then no current flows through the Bit Line to the n amplifier. 8, 16, 32 or more bits are read in parallel depending on the data bus width of the memory. Programming a ‘0’ to the cell is performed by simultaneously pulsing the Bit Line with 5V and the Word Line with 10V; the Program/ Era Controller may have to apply veral puls to program the cell to the correct level. All the cells in a block are erad at the same time; to era a positive voltage (5V) is put on the Source Line and a neg-ative voltage (-8V) is puld on the Word Line; again veral puls may be required to era all the cells correctly.
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AN1266 - APPLICATION NOTE In the NAND architecture a read is performed by connecting the Source Line to ground, raising the voltage level on the Word Line to the n voltage, turning on the correct group of cells using the Bit Line Select and connecting the Bit Line to the n amplifier. The Word Lines of all the other cells in the group are left t to ensure that the cells are in their ‘ON’ state; only the current in the lected state governs the current in the Bit Line, enabling that cell’s contents to be read. Reading a current through a ries of v-eral cells and lect transistors is a slow operation; the random access time is typically 25µs. To program individual cells the Word Line is driven to a very high voltage (15 to 20V) and the Bit Line is connected to ground (0V); the unlected cells have to pass the programming current without being affected them-lves. To era a ctor the Word Lines of the ctor are driven to ground (0V) and the p-well of the c-tor is driven to a very high voltage (15 to 20V).
The higher voltage required in the NAND architecture makes the voltage pumps in the silicon more difficult to design. The management, distribution and switching of the higher voltages is also more difficult. With 0.25µ technology this has not been a limiting factor, but as the technology shrinks the electric fields inside the silicon increa, making it more and more difficult to route the signals through NAND devices. Although the Flash Array is smaller in NAND, the voltage pumps and associated electronics are larger.
CELL DIMENSIONS
When the array is laid out on the silicon wafer there are limitations to the size that each cell can be squashed into. Here the NAND architecture has an advantage over NOR. Figure 5 shows typical layouts for NOR and NAND Flash Memories.
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The silicon area required for the Basic Cell in the NOR configuration is 10F2 (where F is the feature size, related to the technology 0.18µ, 0.15µ etc.); the cell size is limited by the contact to gate dis-tance. The NAND has a smaller configuration, requiring only 6F2, thereby allowing a greater theoretical density of cells for a given technology. However, the decoder area for NAND configurations is much larger than that in NOR configurations, as are the charge pumps; when consi
dering the density as number of cells to the overall Flash memory size, the difference between the two types of configuration is not clear cut in favor of NAND (e Reference [1]).
MULTI-BIT CELLS
The Basic Cell in a Flash Memory can hold different charge levels (quantized only by the charge on a sin-gle electron), giving ri to the possibility of storing more than one bit of information in each Basic Cell. Figure 6 shows the charge level possibilities for a traditional, previous generation Flash Memory and the levels for a 2-bit per cell Multi-Bit Flash Memory. The amount of charge stored determines I DS when the cell is read.
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AN1266 - APPLICATION NOTE NOR architectures have an advantage over NAND in Multi-Bit Cell Flash Memories and are likely to achieve a higher number of bits per cell compared to NAND in the long term. In the NOR architecture the Sen Amplifiers have direct access the each cell. In the NAND architecture the Sen Amplifier’s signal is read through veral other cells; the charge stored in the “read-through” cells makes small, but signifi-cant differences to the value read, decreasing the accuracy. This makes it likely that four bits per cell can-not be achieved in NAND architectures.
Four bits per cell will allow NOR technology to make up the economic difference (in $/Mbyte) lost due to the large cell size. NAND parts with 2-bits per cell are being designed for relea towards the end of the year 2000. NOR parts with 2-bits per cell are already being shipped and 4-bits per cell are planned for late in 2001.
OPERATIONAL DIFFERENCES女士腕表
写给领导的感谢信There are differences in the way that NOR and NAND memories behave at a system level. Table 1 at the end of this ction summarizes the operational differences.
Block, Sector and Page Architecture
Flash Memories cannot era one byte at a time. It is necessary to divide the memory into blocks (or c-tors) of cells that can be erad together. If there is some information stored in the block when the block needs to be erad, it must be moved to another block prior to erasing, otherwi it will be lost. NOR mem-ories offer block sizes between 16 Kbytes and 128 Kbytes. NAND memories offer ctor sizes between 8 Kbytes and 16 Kbytes. (The meaning of the word block and ctor is the same, different suppliers u different terminology).
The page concept is different for NOR and NAND memories. NOR memories with page-mode group up to four address in the same page; the four address take longer for the first access compared to the subquent access within the same page, often it is referred to as “page-mode”.
保重的英文In NAND memories each ctor is sub-divided into pages, usually about 512 bytes long. The read ac
cess time inside the page is fast, whereas jumping to another page is slow. Each page should be programmed as a whole too.
Read Access
NOR Flash Memories offer random access. Parts with access times down to 35ns are available. Page-mode memories are available that offer 150ns access for the first page access and 20ns for the sub-quent access in the page. Burst interfaces allowing bus speeds up to 66Mhz allow NOR memories to be interfaced to a variety of Burst Mode microprocessors.
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NAND Flash Memories offer fast access times for quential reads from within the same page in the mem-ory. The first access to memory in the page typically takes 25µs, with subquent access taking typically 50ns until the end of the page is reached.
Programming
NOR Flash Memories can be programmed in random order, with each program operation taking approx-imately 10µs per byte or word. Multi-Bit Cell memories take longer to program, but include a Program Buff-er that allows parallel programming of many bytes or words, keeping the program rate per word at about 10µs. In the future Multi-Bit Cell NOR Flash Memories will include larger program buffers to reduce the burden on the CPU and decrea the programming time per byte to less than 2µs.
NAND Flash Memories program one page at a time; single byte programming is not possible. A page pro-grams in approximately 200µs and is usually about 512 (or 528) bytes long. The programming rate is about 0.5µs per byte. Multi-Bit Cell NAND Flash Memories take longer to program, approximately 900µs per page or 2µs per byte.
Era
NOR Flash Memories have block sizes between 16 Kbytes and 128 Kbytes. Typically a 64 Kbyte block takes about 0.7s to era. The long era time is due to the need to program each cell in the block to ‘0’before erasing the cells; this operation is required to guarantee that the charge in all the Floating Gates is the same before the era operation begins. In modern Flash Memories the Progra
m/Era Controller manages this process automatically so that the microprocessor can perform other tasks during the era cycle.
NAND Flash Memories typically have block sizes of 16 Kbytes; the take about 2ms to era. NAND Flash Memories do not need to preprogram all their Floating Gates to the same level prior to erasing. Valid Blocks
In NOR Flash Memories 100% of the array is guaranteed to work for a full 100,000 program/era cycles. After 100,000 cycles the probability of a cell failing is still very small. The benefits of having an array that is 100% guaranteed is:
s Storage Algorithms do not need to store information on “bad blocks”, saving space and algorithm development.
s Code can be executed directly from the memory, either for boot purpos (for example in PC systems where the BIOS is in Flash, then is shadowed in RAM) or for both boot and application execution (for example in PDAs where cost and power savings are achieved by executing directly from the Flash and the amount of RAM required is reduced).
In NAND Flash Memories not all of the blocks are guaranteed to work. Typically 98% or more of the Flash Memory is guaranteed. Furthermore it is possible for blocks to fail in rvice, the too need to be marked as “bad”. NAND Flash Memories offer 250,000 program/era cycles, but the are not guaranteed in the same way as NOR Flash.
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