SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM 64Mb H-die SDRAM Specification
Revision 1.4
November 2003
* Samsung Electronics rerves the right to change products or specification without notice.
Rev. 1.4 November 2003
SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM Revision History
Revision 0.0 (May, 2003)
• Target spec relea
Revision 0.1 (July, 2003)
• Preliminary spec relea
Revision 0.2 (August, 2003)
• Modified IBIS characteristic.赞颂母亲的诗
Revision 1.0 (September, 2003)
• Finalized
Revision 1.1 (September, 2003)
• Corrected IBIS Specification.
Revision 1.2 (October, 2003)
• Deleted speed 7C at x4/x8.
Revision 1.3 (October, 2003)
• Deleted AC parameter notes 5.
Revision 1.4 (November, 2003)
• Modified Pin Function description.
Rev. 1.4 November 2003
六字春联SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM
Rev. 1.4 November 2003
Part No.
Orgainization Max Freq.Interface
Package夜莺鸟
K4S640432H-TC(L)7516Mb x 4 133MHz(CL=3)LVTTL
54pin TSOP(II)
K4S640832H-TC(L)758Mb x 8
133MHz(CL=3) K4S641632H-TC(L)604Mb x 16166MHz(CL=3) K4S641632H-TC(L)70143MHz(CL=3) K4S641632H-TC(L)75
133MHz(CL=3)
The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG ′s high perfor-mance CMOS technology. Synchronous design allows preci cycle control with the u of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be uful for a variety of high bandwidth, high performance memory system applications.
懒羊羊经典语录• JEDEC standard 3.3V power supply
成长记忆• LVTTL compatible with multiplexed address • Four banks operation
谨慎性• MRS cycle with address key programs -. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking • Auto & lf refresh
• 64ms refresh period (4K cycle)
GENERAL DESCRIPTION
FEATURES
防疫物资
Ordering Information
4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks Synchronous DRAM
SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM Package Physical Dimension
54Pin TSOP(II) Package Dimension拔牙的危害
Rev. 1.4 November 2003
SDRAM 64Mb H-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.4 November 2003
LWE LDQM
DQi
Samsung Electronics rerves the right to change products or specification without notice.
*
