4.20.21 - 204-Pin EP3-6400/EP3-8500/EP3-10600/EP3-12800 DDR3 SDRAM
72b-S0-DIMM Design Specification
DDR3 SDRAM 72b-SO-DIMM Design Specification Revision 0.05
January 2010
Contents
1. Product Description (3)
2. Environmental Requirements (4)
3. Pinout and Description (5)
4. Component Details (10)
5. DDR3 Registered DIMM Wiring Details (20)
5.1Signal Groups (20)
5.2General Net Structure Routing Guidelines (20)
5.3Signal referencing information (20)
5.4Differential Clock Net Structures (21)挟天子令诸侯
5.5Test Points (21)
5.6Test Point Location (21)
5.7Explanation of Net Structure Diagrams (22)
5.8Net Structure Example (22)
6. Timing Budget (23)
7. On DIMM Thermal Sensor (24)
8. Serial Prence Detect Definition (25)
9. DDR3 DIMM Label Format (27)
10. DIMM Mechanical Specifications (29)
Annex A - Raw Card A ............................................................................................................................TBD Annex B - Raw Card B ............................................................................................................................TBD Annex C - Raw Card C ............................................................................................................................TBD Annex D - Raw Card D ............................................................................................................................TBD
1Product Description
This specification defines the electrical and mechanical requirements for 204-pin, 1.5 Volt, EP3-6400/EP3-8500/EP3-10600/EP3-12800, 72 bit-wide, Double Data Rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (DDR3 SDRAM 72b-SO-DIMMs). The 72b-SO-DIMMs are intended for u as main memory when installed in embedded systems such as telecommunications I/O cards. EP3-6400/EP3-8500/EP3-10600/EP3-12800 refers to the JEDEC standard DIMM naming convention in which EP3-6400/EP3-8500/EP3-10600/EP3-12800 indicates a 204-pin DIMM running at 400/533/666/800 MHz clock speed and offering 6400/8500/10600/12800 MB/s bandwidth on the pri-mary data bus.
Reference design examples are included which provide an initial basis for 72b-SO-DIMM designs which may be unbuf-fered (72b-SO-DIMM), registered (72b-SO-RDIMM), or clocked (72b-SO-CDIMM). Modifications to the reference designs may be required to meet all system timing, signal integrity, and thermal requirements for PC3-6400/PC3-8500/PC3-10600/PC3-12800 support. All registered DIMM implementations must u simulations and lab verification to ensure proper timing requirements and signal integrity in the design.
Table 1 — Product Family Attributes
DIMM organization x72 ECC
DIMM dimensions : height (nom.) x width (nom.) x thickness (max.)
龙福山庄/ MO-number, Variation 30.0 mm x 67.6 mm x 3.80 mm / MO-268, Variation xA 30.0 mm x 67.6 mm x 6.75 mm / MO-268, Variation TBD 30.0 mm x 67.6 mm x 7.55 mm / MO-268, Variation TBD
Pin count204
SDRAMs supported512 Mb, 1 Gb, 2 Gb, 4 Gb, 8 Gb
Ranks supported per DIMM1, 2, 4
Capacity256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB Serial PD Consistent with JC 45
Voltage options 1.5 volt (V DD), 3.3 volt (V DDSPD)
Interface 1.5 volt signal switching bad on reference voltage at VDD/2. See DRAM specification for more detail.
2Environmental Requirements
DDR3 SDRAM 72b-SO-DIMMs are intended for u in telecommunications environments that have limited capacity for heating and air conditioning.
Table 2 — Environmental Parameters
分手情人Symbol Parameter Rating Units Notes T OPR Operating temperature See Note3
H OPR Operating humidity (relative) 10 to 90%Note
T STG Storage temperature -50 to +100°C Note
新年工作展望H STG Storage humidity (without condensation) 5 to 95%Note
P BAR Barometric pressure (operating & storage) 105 to 69K Pascal Note, Note Note 1Stress greater than tho listed may cau permanent damage to the device. This is a stress rating only, and device func-tional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Note 2Up to 9850 ft.
Note 3The designer must meet the ca temperature specifications for individual module components.
3Pinout and Description
Table 3 — Pin Description
Pin Name Description Num-
ber
Pin Name Description
Num-
ber
CK0_t Clock Input, positive line1ODT[1:0] On Die Termination Inputs2 CK0_c Clock Input, negative line1 DQ[63:0] Data Input/Output64 CK1_t Clock Input, positive line1CB[7:0]Data check bits Input/Output8 CK1_c Clock Input, negative line1DQS_t[8:0] Data strobes9 CKE[1:0]Clock Enables2DQS_c[8:0]Data strobes, negative line9冰柜哪个牌子的质量好
RAS_n Row Address Strobe1DM[8:0]Data Masks / Data strobes,
Termination data strobes
9
脱贫成果
CAS_n Column Address Strobe1 WE_n Write Enable1
S_n[3:0]Chip Selects4EVENT_n Rerved for optional hardware temperature nsing
1
设施英语A[9:0],A11,
A[15:13]
Address Inputs14
A10/AP Address Input/Autoprecharge1RESET_n Register and SDRAM control pin1 A12/BC_n Address Input/Burst chop1V DD Power Supply xx BA[2:0] SDRAM Bank Address3V SS Ground xx SCL Serial Prence Detect (SPD) Clock Input1V REFDQ Reference Voltage for DQ1 SDA SPD Data Input/Output1V REFCA Reference Voltage for CA1 SA[1:0]SPD Address Inputs2V TT Termination Voltage2 Par_In Parity bit for the Address and Control bus1V DDSPD SPD Power1
Err_Out_n Parity error found on the Address and
Control bus
1Total204 Table 4 — Registered DIMM Input/Output Functional Description
Symbol Type Polarity Function
CK0_t IN Positive
苹果醋的功效与作用Edge
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock
Driver (72b-SO-RDIMM), on-DIMM PLL (72b-SO-CDIMM), or to DRAMs on rank 0 (72b-SO-DIMM).
CK0_c IN Negative
Edge
Negative line of the differential pair of system clock inputs that drives input to the on-DIMM Clock
Driver (72b-SO-RDIMM), on-DIMM PLL (72b-SO-CDIMM), or to DRAMs on rank 0 (72b-SO-DIMM).
CK1_t IN Positive
Edge
Positive line of a condary differential pair of system clock inputs. Terminated but not ud on 72b-SO-RDIMMs or 72b-SO-CDIMMs. Connected to DRAMs on rank 1 of 72b-SO-DIMMs.
CK1_c IN Negative
Edge
Negative line of a condary differential pair of system clock inputs. Terminated but not ud on
72b-SO-RDIMMs or 72b-SO-CDIMMs. Connected to DRAMs on rank 1 of 72b-SO-DIMMs.
