December 2004
®
3.3V 512K × 32/36 pipelined burst synchronous SRAM
AS7C33512PFS32A AS7C33512PFS36A
Features
•Organization: 524,288 words × 32 or 36 bits •Fast clock speeds to 166 MHz
•Fast clock to data access: 3.4/3.8 ns •Fast
OE access time: 3.4/3.8 ns
•Fully synchronous register-to-register operation •Single-cycle delect
•Asynchronous output enable control •
Available in 100-pin TQFP package
•Individual byte write and global write •Multiple chip enables for easy expansion •3.3V core power supply
•2.5V or 3.3V I/O operation with parate V DDQ •Linear or interleaved burst control
•Snooze mode for reduced power-standby •
Common data inputs and data outputs
Logic block diagram
Selection guide
-166-133Units Minimum cycle time
67.5ns Maximum clock frequency 166133MHz Maximum clock access time 3.4 3.8ns Maximum operating current 300275mA Maximum standby current
9080mA Maximum CMOS standby current (DC)
60
60
mA
Q0Q1512K × 32/36Memory array
Burst logic
CLK CLR CE Address
D
Q
CE CLK DQ d CLK D
Q Byte write registers register DQ c CLK D
Q Byte write registers DQ b CLK D
Q Byte write registers DQ a CLK D
Q Byte write registers Enable CLK
D
Q
register Enable CLK
D Q
delay register CE Output registers Input registers Power down
DQ[a:d]
装修合同范本4
36/32
19
171919
GWE BWE BW d
ADV ADSC ADSP CLK CE0CE1CE2
BW c
BW b
BW a OE孟尝君的故事
ZZ
LBO
OE CLK
CLK
36/3236/32A [18:0]
零基础想学英语16 Mb Synchronous SRAM products list1,2
Org Part Number Mode Speed
1MX18AS7C331MPFS18A PL-SCD166/133 MHz
512KX32AS7C33512PFS32A PL-SCD166/133 MHz
512KX36AS7C33512PFS36A PL-SCD166/133 MHz
1MX18AS7C331MPFD18A PL-DCD166/133 MHz
512KX32AS7C33512PFD32A PL-DCD166/133 MHz
512KX36AS7C33512PFD36A PL-DCD166/133 MHz
1MX18AS7C331MFT18A FT7.5/8.5/10 ns
512KX32AS7C33512FT32A FT7.5/8.5/10 ns
512KX36AS7C33512FT36A FT7.5/8.5/10 ns
1MX18AS7C331MNTD18A NTD-PL166/133 MHz
512KX32AS7C33512NTD32A NTD-PL166/133 MHz
512KX36AS7C33512NTD36A NTD-PL166/133 MHz
1MX18AS7C331MNTF18A NTD-FT7.5/8.5/10 ns
512KX32AS7C33512NTF32A NTD-FT7.5/8.5/10 ns
512KX36AS7C33512NTF36A NTD-FT7.5/8.5/10 ns
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply V oltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD:Pipelined Burst Synchronous SRAM - Single Cycle Delect如何免费获得q币
PL-DCD:Pipelined Burst Synchronous SRAM - Double Cycle Delect
FT:Flow-through Burst Synchronous SRAM
NTD1-PL:Pipelined Burst Synchronous SRAM with NTD TM
NTD-FT:Flow-through Burst Synchronous SRAM with NTD TM
1NTD: No Turnaround Delay. NTD TM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners.
Pin assignment
100-pin TQFP - top view
1 2
3
4 5
6 7
8
9 10 11 12 13
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51 L
B
O A A A A
A
1
A
N
C
N
C
V
S
S
V
D
D A A A A A A A A
3
1
3
2
3
3
3
4
3
5
3
6
3
老君峰7
3
经典战争电影
8
3
9
4
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
1
9
9
9
8
9
7
9
6
9
5
9
4
9
3
9
2
9
1
9
8
9
8
8
8
7
8
6
8
5
8
4
8
3
8
2
8
1
A A C
E
C
E
1
B
W
d
B
W
c
B
W
b
B
W
a
C
E
2
V
D
D
V
S
S
C
L
K
G
W
E
B
W
E
O
E
A
D
S
C
A
D
S
P
A
D
V
A A
TQFP 14 x 20mm
A
NC/DQPc
DQc0
DQc1
V DDQ
V SSQ
DQc2
DQc3
DQc4
DQc5
V SSQ
V DDQ
DQc6
DQc7
NC
V DD
NC
V SS
DQd0
DQd1
V DDQ
赵子龙是怎么死的V SSQ
DQd2
DQd3
DQd4
DQd5
V SSQ
V DDQ
DQd6
DQd7 NC/DQPd DQPb/NC DQb7
DQb6
V DDQ
V SSQ DQb5 DQb4
DQb3 DQb2
V SSQ
V DDQ DQb1 DQb0
V SS
ZZ
DQa7 DQa6
V DDQ
V SSQ DQa5 DQa4 DQa3 DQa2
V SSQ
V DDQ DQa1 DQa0 DQPa/NC V DD
我的情书
NC
Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36 configuration.
Functional description
The AS7C33512PFS32A/36A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as 524,288 words x 32/36. It incorporates a two-stage re
gister-register pipeline for highest frequency on any given technology.Fast cycle times of 6/7.5 ns with clock access times (t CD ) of 3.4/3.8 ns enable 166, and 133 MHz bus frequencies. Three chip enable (CE)inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subquent internally generated burst address.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data accesd by the current address registered in the address registers by the positive edge of CLK are carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asrted, but is sampled on all subquent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is lectable with the LBO input. With LBO unconnected or driven high, burst operations u an interleaved count quence. With LBO driven low, the device us a linear count quence.
Write cycles are performed by disabling the output buffers with OE and asrting a write command.
A global write enable GWE writes all 32/36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more bytes may be written by asrting BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subquent clock edges. Output buffers are disabled when BWn is sampled lOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented internally to the next burst address if BWn and ADV are sampled low. This device operates in single-cycle delect feature during read cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are as follows:
••WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).•Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C33512PFS32A/36A family operates from a core 3.3V power supply. I/Os u a parate power supply that can operate at 2.5V or 3.3V . The devices are available in a 100-pin TQFP package.
TQFP capacitance
* Guaranteed not tested
TQFP thermal resistance
Parameter Symbol Test conditions Min Max Unit Input capacitance C IN *V IN = 0V -5pF I/O capacitance
C I/O *V OUT = 0V
-7pF
Description
Conditions
Symbol Typical Units Thermal resistance (junction to ambient)11 This parameter is sampled
Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51
1–layer θJA 40°C/W 4–layer
θJA 22°C/W Thermal resistance
(junction to top of ca)1
θJC
8
°C/W
Signal descriptions
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is delected and current is reduced to I SB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that caus the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I SB2 is guaranteed after the time t ZZI is met. After entering SNOOZE MODE, all inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during t PUS , only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.
Pin I/O Properties Description
CLK I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.
A,A0,A1I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asrted.DQ[a,b,c,d]I/O SYNC Data. Driven as output when the chip is enabled and when OE is active.
CE0I SYNC Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the “Synchronous truth table” for more information.
CE1, CE2I SYNC Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active.
ADSP I SYNC Address strobe processor. Asrted low to load a new address or to enter standby mode.ADSC I SYNC Address strobe controller. Asrted low to load a new address or to enter standby mode.ADV I SYNC Advance. Asrted low to continue burst read/write.
GWE I SYNC Global write enable. Asrted low to write all 32/36 and 18 bits. When high, BWE and BW[a:d] control write enable.
BWE I SYNC Byte write enable. Asrted low with GWE high to enable effect of BW[a:d] inputs.
BW[a,b,c,d]I SYNC Write enables. Ud to control write of individual bytes when GWE is high and BWE is low. If any of BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d] are inactive, the cycle is a read cycle.
OE I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.LBO I STATIC Selects Burst mode. When tied to V DD or left floating, device follows interleaved Burst order. When driven Low, device follows linear Burst order. This signal is internally pulled High.ZZ I ASYNC
Snooze. Places device in low power mode; data is retained. Connect to GND if unud.NC
-
-
No connect
Write enable truth table (per byte)
Key: X = don’t care, L = low, H = high, n = a, b, c, d; BWE , BWn Asynchronous Truth Table
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwi data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Delected means power down state of which stand-by current depends on cycle times
Burst quence table
Function
GWE BWE BWa BWb BWc BWd Write All Bytes L X X X X X H L L L L L Write Byte a H L L H H H Write Byte c and d H L H H L L Read
H H X X X X H
L
H
H
H
H
Operation ZZ OE
I/O Status Snooze mode
H X High-Z Read
L
L Dout L
H High-Z
Write L X Din, High-Z Delected L
X
High-Z
Interleaved burst address (LBO = 1)
Linear burst address (LBO = 0)
A1 A0A1 A0A1 A0
A1 A0
A1 A0A1 A0A1 A0
A1 A0
Starting Address
0 00 1 1 0 1 1Starting Address 0 00 1 1 0 1 1First Increment 0 10 0 1 1 1 0First Increment 0 1 1 0 1 10 0Second Increment 1 0 1 10 00 1Second Increment 1 0 1 10 00 1Third Increment 1 1 1 00 10 0Third Increment 1 1 1 00 1 1 0
