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EtronTech EM638165
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Bad Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671
4Mega x 16 Synchronous DRAM (SDRAM)
Preliminary (Rev 0.6, 2/2001)
Features
• Fast access time from clock: 5/6/6/6/7 ns • Fast clock rate: 166/143/133/125/100 MHz • Fully synchronous operation • Internal pipelined architecture • 1M word x 16-bit x 4-bank • Programmable Mode registers - CAS# Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst stop function
• Auto Refresh and Self Refresh • 4096 refresh cycles/64ms • CKE power down mode
• Single +3.3V ± 0.3V power supply • Interface: LVTTL
• 54-pin 400 mil plastic TSOP II package云的英语怎么说
Overview
The EM638165 SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured as 4 Banks of 1M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write access to the SDRAM are burst oriented; access start at a lected location and continue for a programmed number of locations in a programmed quence. Access begin with the registration of a BankActivate command which is then followed by a Read or Write command.
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The EM638165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a lf-timed row precharge that is initiated at the end of the burst quence. The refresh functions, either Auto or Self Refresh are easy to u.
By having a programmable mode register, the system can choo the most suitable modes to maximize its performance. The devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications.
Pin Assignment (Top View)
Key Specifications
EM638165
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t CK3 Clock Cycle time(min.)
6/7/7.5/8/10 ns t AC3 Access time from CLK(max.) 5/5.4/5.4/6/7 ns
t RAS Row Active time(max.) 42/45/45/48/50 ns t RC Row Cycle time(min.)国画交易
60/63/68/70/80 ns
Ordering Information
Part Number Frequency Package EM638165TS-6 166MHz TSOP II EM638165TS-7 143MHz TSOP II EM638165TS-7.5 133MHz TSOP II EM638165TS-8 125MHz TSOP II EM638165TS-10
100MHz
TSOP II
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EtronTech EM638165
Block Diagram
R E COUNTER
ADDRESS
BUFFER
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EtronTech EM638165
Pin Descriptions
Table 1. Pin Details of EM638165
Symbol Type Description
CLK
古诗《所见》Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers.
CKE Input
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes low synchronously with clock(t-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh modes, providing low standby power.
Bank Select: BA0,BA1 input lect the bank for operation.
BA1 BA0 Select Bank 0 0 BANK #A 0 1 BANK #B
1 0 BANK #C BA0,BA1 Input
1
1
BANK #D
A0-A11 Input
Address Inputs: A0-A11 are sampled during the BankActivate command (row address A0-A11) and Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to lect one location out of the 2M available in the respective bank. During a Precharge command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH). The address inputs also provide the op-code during a Mode Register Set command.
CS# Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external bank lection on systems with multiple banks. It is considered part of the command code.
RAS# Input
圣家族教堂Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS# are asrted "LOW" and CAS# is asrted "HIGH," either the BankActivate command or the Precharge command is lected by the WE# signal. When the WE# is asrted "HIGH," the BankActivate command is lected and the bank designated by BS is turned on to the active state. When the WE# is asrted "LOW," the Precharge command is lected and the bank designated by BS is switched to the idle state after the precharge operation.
CAS# Input
Column Address Strobe: The CAS# signal defines the operation commands in conjunction with the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is held "HIGH" and CS# is asrted "LOW," the column access is started by asrting CAS# "LOW." Then, the Read or Write command is lected by asrting WE# "LOW" or "HIGH."
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EtronTech EM638165 WE# Input Write Enable: The WE# signal defines the operation commands in conjunction
with the RAS# and CAS# signals and is latched at the positive edges of CLK.
The WE# input is ud to lect the BankActivate or Precharge command and
Read or Write command.
LDQM, UDQM Input Data Input/Output Mask: Controls output buffers in read mode and masks Input data in write mode.
DQ0-DQ15 Input /
Output Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of CLK. The I/Os are maskable during Reads and Writes.
NC/RFU - No Connect: The pins should be left unconnected.
V DDQ Supply DQ Power: Provide isolated power to DQs for improved noi immunity.
青海特色小吃
( 3.3V± 0.3V )
V SSQ Supply DQ Ground: Provide isolated ground to DQs for improved noi immunity.
( 0 V )
V DD Supply Power Supply: +3.3V ± 0.3V
V SS Supply Ground
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