A High-Speed Energy-Efficient Segmented Prequantize and Bypass DAC for SAR ADCs Xiaoyang Wang,Xiong Zhou,and Qiang Li,Senior Member,IEEE
Abstract—This brief prents an energy-efficient high-speed digital-to-analog converter structure that is implemented in a 10-bit150-MS/s successive approximation register(SAR)analog-to-digital converter(ADC).To reduce energy consumption and improve ADC linearity,a gmented prequantize and bypass architecture is propod to avoid unnecessary switching of high-weight capacitors bad on the results of prequantization.To elimi-nate possible conversion error caud by parasitic capacitance and provide redundancy,two extra capacitors are inrted.A proto-type10-bit150-MS/s SAR ADC with the propod architecture is implemented in a standard65-nm CMOS technology.According to the simulation,the ADC achieves a spurious-free dynamic range of83.64dB and an effective number of bits of9.52bits with only 1.20mW power consumption at a1.2-V supply,resulting in a figure of merit of10.9fJ/conversion-step.
Index Terms—Analog-to-digital converter(ADC),energy-efficient,successive approximation register(SAR).
I.I NTRODUCTION
S UCCESSIVE approximation register(SAR)analog-to-digital converter(ADC)’s mainly digital structure makes it require the minimum static current dissipation and contin-uously benefit from the CMOS technology downscaling.The time-interleave(TI)SAR architecture has become a low-power counterpart to pipeline ADCs,which are often considered for high-speed applications[1].Increasing the speed and decreas-ing the power consumption of subchannel ADCs can signifi-cantly improve the overall performance of the TI-SAR ADC. For high-resolution SAR ADC,the exponentially incread capacitors make capacitors’switching occupy a considerable part of the total power consumption.The largest capacitor is equal to2N−2times of the unit capacitor[2],[3],where N is the resolution of the ADC.The majority of the switching power is dissipated in conversions of MSB codes where high-weight capacitorsflip[4].The major limitations for the speed of SAR ADCs lie in three aspects:ttling speed of digital-to-analog converter(DAC),yielding time of comparator,and digital logic delay.For medium-resolution SAR ADCs,the digital logic delay can be eliminated by improving the architecture[5].How-
Manuscript received February9,2015;accepted April8,2015.Date of publication May21,2015;date of current version July24,2015.This work was supported in part by the National Natural Science Foundation of China under Grant61006027,by the New Century Excellent Talents Program of China
under Grant NCET-10-0297,and by the National Program for Support of Top-Notch Young Professionals(First Batch).This brief was recommended by Associate Editor P.Rombouts.
The authors are with the Integrated Systems Laboratory,School of Micro-electronics and Solid-State Electronics,University of Electronic Science and Technology of China,Chengdu610054,China(e-mail:qli@uestc.edu). Color versions of one or more of thefigures in this brief are available online at ieeexplore.ieee.
Digital Object Identifier
10.1109/TCSII.2015.2435432Fig.1.Architecture of the gmented SAR ADC.
ever,this method needs N comparators for N-bit conversion and an extra offt cancellation circuit.For high-resolution SAR ADCs,the charge redistribution time for the large capaci-tors is much longer than the small capacitors.To make the ADC operate correctly,the period of1-bit conversion must be larger than the ttling time for high-weight capacitors,but this would cau a waste of time when low-weight codes are converted using small capacitors.
In this brief,a high-speed energy-efficient gmented pre-quantize and bypass SAR structure is propod.By gmenting capacitive DAC into two parts,MSB codes are converted using small capacitors,and enough time is rerved for the ttling of large capacitors.Unnecessary switching of high-weight capac-itors is avoided,and energy efficiency and linearity of the ADC are both improved.A similar concept is ud in[6],but an extra comparator and coar DAC are ud,which add extra area and circuit complexity.
paper可数还是不可数II.S EGMENTED P REQUANTIZE AND
B YPASS SAR A RCHITECTURE
Fig.1shows the propod gmented prequantize and bypass SAR ADC,including a comparator,gmented capacitive DAC, and digital controlling logic.The actual design is differential, whereas thefigure shows a single-ended design for simplicity. The propod architecture parates the conventional capacitor array into two parts by switch K3:the left array with high-weight capacitors and the right array with lower weight ones. The whole array is connected to the comparator at the top plate of the right array so that small capacitors can be exploited to quantize the residual voltage during MSB codes’conversion cy-cles.To keep the common-mode voltage relatively stable and avoid using the reference voltage V cm,every capacitor,except the LSB one,is split into two identical small capacitors and con-nected to V ref and GND,respectively[7].As the LSB capacitor is not split,the unit capacitor can still keep the same value as the conventional one and does not increa the unit capacitor’s
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mismatch.For the decision of the last bit,as the LSB cap is not split,the common-mode voltage will ch
ange about0.5LSB. However,since this value is small and occurs in the last bit,its impact on the dynamic offt and ADC performance can be very small.To eliminate the possible error caud by capacitor mismatch and parasitic between left and right arrays,equi-librium and compensation capacitors are inrted to the left array.The equilibrium capacitor is ud to balance the parasitic weight between the two arrays,and the compensation capacitor provides a redundant bit to compensate the residual voltage. A.Prequantize and Bypass Concept
The key working principle of SAR ADC is to compare the in-put signal with DAC’s output successively and generate a code each cycle.This procedure ensures SAR ADC has a simple struc-ture but can also introduce some unnecessary switching.After sampling,a feedback voltage is produced by DAC(usually V ref/2),and it is compared with the input signal.If the sampled signal is smaller than DAC’s output,SAR logic controls the capacitive DAC to decrea its output by half;otherwi,the output of DAC will be added by V ref/4.For example,the quan-tization range of a6-bit SAR is from−32to+32LSB.When a signal of5LSB is sampled,the DAC will switch and approxi-mate the input,such as5=+16−8−4+2−1(LSB).The last comparison between the DAC output and the sampled signal will determine whether the input is in the range of4–5or 5–6.This procedure is correct but brings about some unneces-sary switching.If DAC’s current output voltage is less than that of the
previous cycle,it means that DAC’s output is excessive last time.In the conversion given above,the minus of8,4, and1actually imply that their former weights16,8,and2do not need to take part in the conversion.Thus,the input can be reprented again by5=0+0+4+0+1,which switches only two low-weight capacitors instead of all thefive.
For gmented prequantize and bypass SAR,the capacitor array is gmented into two parts,and small capacitors are ud to prequantize the MSB codes.Whether high-weight capacitors need to be switched is determined by the codes we get from the prequantization pha.Unnecessary switchings are bypasd, which improves power efficiency and linearity of the ADC. The bypass window technique propod in[8]can also be energy efficient and can suppress the peak INL and DNL values. However,only the signal falling into the window can be by-pasd;thus,the working efficiency strongly depends on the window size and the value of the input signal.Moreover,to form the window and detect the input signal,two additional comparators and a reference voltage are needed.Compared with the bypass window technique,the prequantization and by-pass SAR can have a global optimization regardless of the value of the input signal,and no additional components are needed, except two switches.
B.Working Principle
The operation of the propod SAR can be divided into two phas for each conversion period:1)prequantization and bypass and2)residual quantization.The conversion begins with sampling.First,switches K1–K3clo,and the input signal
is Fig.2.Switching procedure of the gmented prequantize and bypass SAR ADC.
sampled on the top plate of both left and right arrays,as shown in Fig.2(a).Then K1,K2,and K3turn off,and the conversion goes into the prequantization mode.As K3is off,the right array together with the comparator and controlling logic forms a nor-mal5-bit ADC,which is employed to convert the higher weight 5-bit codes of the propod10-bit ADC.The dynamic com-parator compares the input signal and gets the MSB code.Ac-cording to the MSB code,the digital logic controls the highest weight capacitor in the right array,namely,C3,to switch to the corresponding reference voltage.Then,after the right capac-itive DAC ttles within1/2LSB,the comparator starts the cond comparison.C2is switched bad on the result of the cond comparison.C8is switched bad on the result of both first and cond comparisons.If the cond code is different from the MSB code,it means that the DAC has an excess output last time and the MSB capacitor(C8)is bypasd.C8just keeps the same state as it is ,connects to the same reference voltage at the sampling pha.Therefore,the DAC output volt-age contributed by C8is0.Otherwi,the DAC’s output is not enough,and C8is switched and contributes an output voltage of its corresponding weight.This procedure continues until all the states of C8−C5in the left array are determined,as shown in Fig.2(b).Finally,C4is switched according to the MSB code as DAC’s initial output of the residual quantization pha.
After thefirstfive codes are obtained and the capacitors in the left array are properly t,K3is clod,and all capacitors in the right array are ret to the initial condition.The codes applied to the capacitors return to their starting values.The ADC returns to a normal10-bit SAR ADC who higher weight5-bit codes have been converted.Then the residual quantization pha starts,as shown in Fig.2(c).The switching procedure next is just like the conventional SAR,except a compensation cycle[9] is added,which is ud to compensate the possible error caud by the mismatch and parasitic difference between left and right arrays.The lower weight5-bit codes and compensation code D5b are converted subquently.
Fig.3.Parasitic capacitance in the left and right DAC
arrays.
Fig.4.Error caud by parasitic capacitance weight difference and correction technique.
III.E RROR C ORRECTION AND P ERFORMANCE I MPROVEMENT
一朵花开的时间As parasitic capacitance weights differently between right and left arrays,errors may occur when high-weight codes are transferred to the left array.In Fig.3,C pL and C pR reprent the total parasitic capacitance at the output of the left and right DAC arrays,,
C pL =C K 2+C K 3+C wL
(1)C pR =C K 3+C K 1+C CMP +C wR
(2)
硕大无朋
where C K 1−C K 3are the parasitic capacitance introduced by switches K 1−K 3.C wL and C wR are parasitics from the wire layout and the top plate of capacitors.The input transistors of the comparator also contribute the capacitance C CMP .In ideal conditions,C 3should weight half of the right array just as the largest capacitor C 8weights half of the whole array.As the total capacitance of the whole array is much larger than that of the right array,parasitic capacitance weights differently between the left and right arrays.Therefore,the output of the right array DAC has a voltage shrink compared with t
hat of the whole ar-ray.For example,if a signal is sampled,the conventional SAR will approximate it and get the code “10111,”as shown in Fig.4(a).For the right array DAC,as there is voltage attenua-tion caud by parasitic capacitance,SAR will approximate it,as shown Fig.4(b),and get the code “11000.”If we apply this code to the whole array directly,the DAC output will be as in Fig.4(c),and an error occurs.
To solve this problem,equilibrium capacitor (C E )and com-pensation capacitor (C C )are inrted.C E is connected to GND so that it can balance the parasitic weight between the left and right arrays.Its value can be obtained by calculation with pa-rameters from layout extraction.For the capacitors in the left and right DAC arrays to have the same weight,they should have the following relationship:
C R C R +C pR =C L +C R
C L +C R +C pL +C pR +C E .(3)
That is
C R =
C L
C R
·C pR −C pL =31C pR −C pL .(4)
Substituting for C pL and C pR from (1)and (2),we can get C E =31·(C K 3+C K 1+C CMP +C wR )−C K 2+C K 3+C wL .
(5)The value of C pL and C pR can be obtained from layout extraction.If the value of C E is correctly chon,parasitic capacitance weights the same between the left and right arrays,and the code transfer will have no error.In addition to the parasitic,other factors such as mismatch and noi may also cau code error in the first five comparisons.Considering the inaccuracy caud by process variation,parameter extraction,and other factors,a compensation capacitor C C is inrted to provide redundancy.In the previous condition,after the first 5-bit code conversion,the DAC’s output is not convergent with the input signal.To make the conversion correct,C C provides a compensation voltage,as shown in Fig.4(d),and later,the remaining 5-bit codes further approximate the input signal and finally achieve a successful conversion.Considering both the power and the ef-fectiveness of compensation,a capacitor that is equal to 8C 0is inrted as C C ,which can tolerate a 3.125%parasi
tic difference between the left and right arrays.
As the right array is just ud to convert the 5MSB codes and the codes are transferred to the whole array,the final DAC out-put is provided by the whole array,and its accuracy satisfies the 10-bit requirement.In this design,the compensation capacitor has a value of 8C 0;thus,the accuracy requirement of the coar ADC is 6bits.After calculation,both the whole array and the small DAC can satisfy the mismatch and noi (sampling noi,DAC noi,and comparator noi)requirements.With adequate redundancy,the possible code error caud by noi,mismatch,and parasitic capacitance variation during the first five comparisons can be calibrated.
As K 3connects the left and right arrays and locates in the critical path,its resistance will influence the ttling speed.To improve the overall conversion speed,a voltage-boosting switch is ud,which significantly reduces the ON -resistance of K 3.
IV .P ROPERTIES OF S EGMENTED P REQUANTIZE
AND B YPASS SAR A.Speed Improvement
The gmented bypass structure can substantially increa the conversion speed.In the propod ADC architecture,when we convert the first 5-bit code,small capacitors are ud instead
Fig.5.Timing diagram of the gmented bypass SAR.
of the large ones,so that the capacitive DAC ttles much faster [10].Suppo the time required for the largest capacitor in the whole array (C 8)to ttle within 1/2LSB is t C .To convert a 1-bit code,the time for the conventional binary SAR ADC and the gmented bypass SAR ADC are T con and T ,respectively.As C 2and C 8are switched at the same time,the time for the largest capacitor C 8to ttle is 3T ,as shown in Fig.5.It can be obtained that
3·T =t c <T con
=>
T <
T con
3
.(6)From the preceding equation,it can be obrved that the pro-pod SAR can ttles three times faster than the conventional binary SAR for 1bit cycling theoretically.
Compared with the conventional binary SAR ADC,the pro-pod architecture can also reduce the siz
e of the reference switches and buffers.As the timing requirement for the high-weight capacitors is relaxed,smaller buffers can be ud to drive the switches connected at the bottom plates of large capacitors in the left array,which can reduce the driver’s power consumption.
B.Power Analysis
The power consumption of SAR ADCs consists of four parts:1)DAC switching;2)DAC switch buffers;3)successive ap-proximation control logic;and 4)comparator and bootstrap switches.The propod SAR ADC needs extra control logic to determine whether the switching of MSB capacitors can be bypasd.However,the additional control logic is simple,and only veral logic gates are needed.The size of each switch and switch buffer are binary weighted like the capacitor array.The power consumption of switch buffers is proportional to the switch sizes.Thus,the switching of high-weight capacitors do-minates the majority of power consumption in parts 1)and 2).In the propod SAR architecture,when unnecessary switch-ings are detected and bypasd,power consumption of parts 1)and 2)can be reduced significantly.
The behavioral simulation of switching energy versus output codes for Monotonic [3],MCS [2],and MCS with the propod switching method is shown in Fig.6.The average switching energy of MCS w
设计准则
ith the propod structure is 74.2CV 2,which is about 43.6%of the original MCS (170.2CV 2)and 29%of Monotonic (255.5CV 2).As the signal around V ref /2is converted all by small capacitors and large capacitors keep still,it can be obrved that the switching energy around the middle of the codes is the least.For the signal who amplitude is clo to +/−V ref ,all capacitors take part in the quantization,and the energy is approximately the same as
MCS.
Fig.6.Switching energy versus output
codes.
Fig.7.Simulated INL plots (1000times)for MCS and MCS with propod architecture with capacitor mismatch 3σ0=6%.
C.Linearity Property
Typically,the dominant error source that deteriorates the linearity of high-resolution SAR ADCs is the DAC capacitor mismatch.Suppo the error distribution of unit capacitors is independent and identically distributed Gaussian random varia-bles.The k th capacitor in the DAC consists of 2k unit c
apac-itors and has an error term of δk ;therefore,the error voltage contributed by the k th capacitor is
V error _k =
δk
n −1
i =1
C i
一道本影院·V ref
(7)
where C i is the i th capacitor in the DAC,V ref is the reference voltage,and δk is the error term of the k th capacitor.The va-riance of the error term is打字谜
E δ2k
=2k ·σ20·C 2
0(8)where σ2
is the variance of the unit capacitor.From (7)and (8),it can be obtained that the higher weight capacitor introduces more error voltage to DAC’s output.During prequantization and bypass pha of the propod SAR,if switchings of MSB
Fig.8.8192-point FFT spectrums for Nyquist and10-MHz input. capacitors are bypasd,their mismatch will not affect DAC’s output,which ameliorate ADC’s linearity.
For THE conventional SAR ADC,the maximum INL occurs during V ref/2transition.This is becau when codes translate from011..11to100..00,all capacitors’mismatch takes part in DAC’s output,and there will be a middle-code glitch in the ADC’s static performance plot.However,for the propod SAR,as signals near V ref/2are converted by small capacitors, the middle-code glitch disappears.Fig.7shows the ADC INL simulation results for MCS and MCS with the propod switching method in MATLAB.The mismatch for capacitors in the DAC is randomly generated with3σ0=6%for1000times. Simulation results show that the propod architecture results in a notch at middle code and the ADC’s overall linearity has been improved.
V.S IMULATION R ESULTS
The propod10-bit SAR ADC is designed in65-nm CMOS technology.The sampling rate of the gmented prequantize and bypass SAR ADC is150MHz at a1.2-V supply.Considering power consumption,limitation of the switching noi,and capa-citor mismatch,the unit capacitor is chon to be about3fF. Fig.8shows the8192-point fast Fourier transform(FFT)plot of the ADC output at transistor-level simulation with transient noi.At a sampling rate of150MS/s,the ADC achieves an ef-fective number of bits(ENOB)of9.52bits at10MHz and 9.47bits at73MHz.The spurious-free dynamic ranges(SFDRs) are83.64and82.10dB,respectively.The total power consump-tion is about1.201mW.Evaluated by thefigure-of-merit(FOM) equation defined as Power/(2ENOB∗f s),the ADC achieves 10.9fJ/conversion-step.
VI.C ONCLUSION
In this brief,a gmented prequantize and bypass architecture for SAR ADC has been propod.The charge-redistribution DAC is parated into two parts,and a small DAC array is uti-lized to convert the MSB codes.Bad on the result of prequan-tization,unnecessary switching of high-weight capacitors is bypasd,which improves the power efficiency and linearity of ADC and accelerates the conversion speed.A10-bit150-MS/s ADC with the propod architecture has been implemented with a65-nm CMOS technology at a 1.2-V supply.The prototype performs an ENOB of9.52bits and an SF
DR of 83.64dB at transistor-level simulation,achieving a FOM of 10.9fJ/conversion-step.
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