2.0-18.0 GHz GaAs MMIC Low Noi Amplifier
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Self Bias Architecture
On-Chip Drain Bias Coil/DC Blocking 9.0 dB Small Signal Gain 4.5 dB Noi Figure
+19.0 dBm P1dB Compression Point
乡村小镇100% Visual Inspection to MIL-STD-883
Method 2010
General Description
Supply Voltage (Vd)Supply Current (Id)Input Power (Pin)
Storage Temperature (Tstg)Operating Temperature (Ta)Channel Temperature (Tch)
+8.5 VDC 175 mA +20 dBm
-65 to +165 O C -55 to MTTF Table MTTF Table Chip Device Layout
(1) Channel temperature affects a device's MTTF. It is recommended to keep channel temperature as low as possible for maximum life.
1
1Mimix Broadband’s 2.0-18.0 GHz GaAs MMIC
distributed low noi amplifier has a small signal gain of 9.0 dB with a noi figure of 4.5 dB across the band. This MMIC us Mimix Broadband’s 0.3 µm GaAs PHEMT device model technology, and i
s bad upon optical beam lithography to ensure high repeatability and uniformity. The chip has surface passivation to protect and provide a rugged part with backside via holes and gold metallization to allow either a
宫非宫
conductive epoxy or eutectic solder die attach process. This device is well suited for fiber optic, microwave radio, military, space, telecom infrastructure, test instrumentation and VSAT applications.
o Absolute Maximum Ratings
July 2006 - Rev 06-Jul-06
100% on-wafer DC testing and 100% RF wafer qualification. Wafer qualification includes sample testing from each quadrant with an 80% pass rate required.
Low Noi Amplifier Measurements
2.0-18.0 GHz GaAs MMIC Low Noi Amplifier
July 2006 - Rev 06-Jul-06
Low Noi Amplifier Measurements (cont,)
2.0-18.0 GHz GaAs MMIC Low Noi Amplifier
July 2006 - Rev 06-Jul-06
S-Parameters
2.0-18.0 GHz GaAs MMIC Low Noi Amplifier
Typical S-Parameter Data for CMM4000V d=5.0 V Id=110 m A Frequency S11S11S21S21S12S12S22S22(GHz)(Mag)(Ang)(Mag)(Ang)(Mag)(Ang)(Mag)(Ang)0.10.939-28.860.030117.390.000133.120.983118.741.00.364-132.15 1.904-171.740.005-60.120.534-87.112.00.296-154.45 2.668-105.500.010-5.710.229-64.483.00.286-160.46 2.828-70.660.01818.160.160-81.404.00.292-165.78 2.828-44.410.02244.370.185-91.055.00.315-170.64 2.797-22.200.02664.720.209-89.286.00.320-179.10 2.736-1.450.03076.120.225-84.507.00.290174.17 2.74116.880.03697.100.225-74.338.00.266167.95 2.74035.360.040112.340.212-65.509.00.228162.72 2.76253.730.045127.570.188-56.2210.00.181161.86 2.80672.320.050143.050.153-46.4811.00.144170.52 2.86291.580.056159.350.108-37.1112.00.139-173.68 2.911111.730.062176.770.056-30.8113.00.17
1-168.09 2.934132.750.068-164.720.014-113.4814.00.194-177.47 2.900154.420.072-145.030.068-151.5215.00.190164.69 2.814175.340.075-126.550.112-133.1416.00.159135.47 2.816-164.760.080-108.430.099-114.0417.00.12077.24 2.903-141.370.087-87.590.077-134.2118.00.1480.06 2.899-115.020.092-63.430.106-143.6419.00.191-50.22 2.832-86.800.095-37.360.113-137.8220.00.103-69.38 2.720-53.340.096-5.720.089-152.9321.00.305-2.05 2.171-11.920.08034.730.166-175.5722.00.623-38.06 1.30221.150.04866.500.241-156.7723.00.768-63.850.76440.260.02985.110.254-141.6824.00.840-81.230.47552.760.01792.790.243-132.2525.00.878-93.970.30360.920.010100.580.227-127.3726.00.908-103.830.19761.870.00693.670.209-126.4127.00.927-112.290.14753.600.00560.510.201-128.7828.00.939-119.490.14848.150.00751.590.204-132.3629.00.941-125.430.15855.220.00768.770.219-134.5030.0
0.946
-130.57
0.155
69.84
0.008
84.14
0.238
-132.64
July 2006 - Rev 06-Jul-06
Mechanical Drawing
Bias Arrangement
(Note: Engineering designator is M393)
Units: millimeters (inches) Bond pad dimensions are shown to center of bond pad.
三孩政策Thickness: 0.076 +/- 0.010 (0.003 +/- 0.0004), Backside is ground, Bond Pad/Backside Metallization: Gold All DC Bond Pads are 0.080 x 0.080 (0.003 x 0.003). All RF Bond Pads are 0.180 x 0.080 (0.007 x 0.003).
Bond pad centers are approximately 0.109 (0.004) from the edge of the chip.Dicing tolerance: +/- 0.005 (+/- 0.0002). Approximate weight: 1.172 mg
Bond Pad #1 (RF In)Bond Pad #2 (Vd)
Bond Pad #3 (RF Out)
Bond Pad #4 (Rs-8.5 )
Bond Pad #5 (Rs-12 )
Bond Pad #6 (Rs-13 )
2.0-18.0 GHz GaAs MMIC
Low Noi Amplifier
1.000(0.039)
0.348
生日发多少红包
(0.014)
餐饮娱乐
0.0
0.0
(0.074)
(0.066)1.414(0.056)
0.539(0.021)
3
1
4
6Vd
RF In
RF Out
July 2006 - Rev 06-Jul-06
Page 6 of 7
App Note [1] Biasing - As shown in the bonding diagram, this device operates using a lf-biad architecture and only requires one drain bias. Bias is nominally Vd=5V, I=115mA. Additionally there are three source resistors on chip, 13, 12 and 8.5 Ohms. One of the must be bonded to ground. Typically 12 Ohms is bonded to ground to achieve performance as shown. Bonding to one of the other resistors or any or all in parallel may allow additional performance adjustment.
App Note [2] Bias Arrangement - Each DC pad (Vd) needs to have DC bypass capacitance (~100-200 pF) as clo to the device as possible.Additional DC bypass capacitance (~0.01 uF) is also recommended.
Device Schematic
MTTF T able (TBD) (Thermal Resistance (Rth) is 82ºC/W)
Backplate Temperature 55 deg Celsius 75 deg Celsius 95 deg Celsius
Channel Temperature deg Celsius deg Celsius deg Celsius
FITs E+E+E+
MTTF Hours孕妇可以吃乌梅吗
E+E+E+
Rth C/W C/W C/W
Bias Conditions: Vd=5.0V, Id=115 mA
The numbers were calculated bad on accelerated life test information and thermal model analysis received from the fabricating foundry.
2.0-18.0 GHz GaAs MMIC Low Noi Amplifier
July 2006 - Rev 06-Jul-06
