MT-008
TUTORIAL Converting Oscillator Pha Noi to Time Jitter
by Walt Kester
INTRODUCTION
A low aperture jitter specification of an ADC is critical to achieving high levels of signal-to-noi ratios (SNR). (See References 1, 2, and 3). ADCs are available with aperture jitter specifications as low as 60-fs rms (AD9445 14-bits @ 125 MSPS and AD9446 16-bits @ 100 MSPS). Extremely low jitter sampling clocks must therefore be utilized so that the ADC performance is not degraded, becau the total jitter is the root-sum-square of the internal converter aperture jitter and the external sampling clock jitter. However, oscillators ud for sampling clock generation are more often specified in terms of pha noi rather than time jitter. The purpo of this discussion is to develop a simple method for converting oscillator pha noi into time jitter.
PHASE NOISE DEFINED
First, a few definitions are in order. Figure 1 shows a typical output frequency spectrum of a non-ideal o
scillator (i.e., one that has jitter in the time domain, corresponding to pha noi in the frequency domain). The spectrum shows the noi power in a 1-Hz bandwidth as a function of frequency. Pha noi is defined as the ratio of the noi in a 1-Hz bandwidth at a specified frequency offt, f m, to the oscillator signal amplitude at frequency f O.
o m
Figure 1: Oscillator Power Spectrum Due to Pha Noi
The sampling process is basically a multiplication of the sampling clock and the analog input signal. This is multiplication in the time domain, which is equivalent to convolution in the frequency domain. Therefore, the spectrum of the sampling clock oscillator is convolved with the input and shows up on the FFT output of a pure sinewave input signal (e Figure 2).
f o
f s
f o
IDEAL SINEWAVE
INPUT SAMPLING CLOCK WITH PHASE NOISE
FFT OUTPUT FOR IDEAL ADC WITH N →∞(MEASURED FROM DC TO f s /2)SNR = 20log 101
2πf o t j f f
Figure 2: Effect of Sampling Clock Pha Noi Ideal Digitized Sinewave
The "clo-in" pha noi will "smear" the fundamental signal into a number of frequency bins, thereby reducing the overall spectral resolution. The "broadband" pha noi will cau a degradation in the overall SNR as predicted by Eq. 1 (Reference 1 and 2):
⎥⎥⎦
⎤
⎢⎢⎣⎡π=j 10t f 21log 20SNR .
Eq. 1
弩箭It is customary to characterize an oscillator in terms of its single-sideband pha noi as shown in Figure 3, where the pha noi in dBc/Hz is plotted as a function of frequency offt, f m , with the frequency axis on a log scale. Note the actual curve is approximated by a number of regions, each having a slope of 1/f x , where x = 0 corresponds to the "white" pha noi region (slope = 0 dB/decade), and x = 1 corresponds to the "flicker" pha noi region (slope = –20 dB/decade). There are also regions where x = 2, 3, 4, and the regions occur progressively clor to the carrier frequency.
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET, f m , (LOG SCALE)
Figure 3: Oscillator Pha Noi in dBc/Hz vs. Frequency Offt
Note that the pha noi curve is somewhat analogous to the input voltage noi spectral density of an amplifier. Like amplifier voltage noi, low 1/f corner frequencies are highly desirable in an oscillator.
We have en that oscillators are typically specified in terms of pha noi, but in order to relate pha noi to ADC performance, the pha noi must be converted into jitter. In order to make the graph relevant to modern ADC applications, the oscillator frequency (sampling frequency) is chon to be 100 MHz for discussion purpos, and a typical graph is shown in Figure 4. Notice that the pha noi curve is approximated by a number of individual line gments, and the end points of each gment are defined by data points.
FREQUENCY OFFSET (Hz)PHASE
NOISE
(dBc/Hz)f m
Figure 4: Calculating Jitter from Pha Noi
CONVERTING PHASE NOISE TO JITTER
The first step in calculating the equivalent rms jitter is to obtain the integrated pha noi power over the frequency range of interest, i.e., the area of the curve, A. The curve is broken into a number of individual areas (A1, A2, A3, A4), each defined by two data points. Generally speaking, the upper frequency range for the integration should be twice the sampling frequency, assuming there is no filtering between the oscillator and the ADC input. This approximates the bandwidth of the ADC sampling clock input.
Selecting the lower frequency for the integration also requires some judgment. In theory, it should be as low as possible to get the true rms jitter. In practice, however, the oscillator specifications generally will not be given for offt frequencies less than 10 Hz, or so—however, this will certainly give accurate enough results in the calculations. A lower frequency of integration of 100 Hz is reasonable in most cas, if that specification is available. Otherwi, u either the 1-kHz or 10-kHz data point.
One should also consider that the "clo-in" pha noi affects the spectral resolution of the system, while the broadband noi affects the overall system SNR. Probably the wist approach is to integrate each area parately as explained below and examine the magnitude of the jitter contribution of each area. The low frequency contributions may be negligible compared to the broad屡教不改的意思
band contribution if a crystal oscillator is ud. Other types of oscillators may have significant jitter contributions in the low frequency area, and a decision must be made regarding their importance to the overall system frequency resolution.
The integration of each individual area yields individual power ratios. The individual power ratios are then summed and converted back into dBc. Once the integrated pha noi power is known, the rms pha jitter in radians is given by the equation (e References 3-7 for further details, derivations, etc.),
10/A 102)radians (Jitter Pha RMS ⋅=,
Eq. 2
and dividing by 2πf O converts the jitter in radians to jitter in conds:
O
10
纣王姓什么/A f 2102)onds (c Jitter Pha RMS π⋅=
.
Eq. 3
It should be noted that computer programs and spreadsheets are available online to perform the integration by gments and calculate the rms jitter, thereby greatly simplifying the process (References 8, 9).
Figure 5 shows a sample calculation which assumes only broadband pha noi. The broadband pha noi chon of –150 dBc/Hz reprents a reasonably good signal generator specification, so the jitter number obtained reprents a practical situation. The pha noi of –150 dBc/Hz (expresd as a ratio) is multiplied by the bandwidth of integration (200 MHz) to obtain the integrated pha noi of –67 dBc. Note that this multiplication is equivalent to adding the
quantity 10 log 10[200 MHz – 0.01 MHz] to the pha noi in dBc/Hz. In practice, the lower frequency limit of 0.01 MHz can be dropped from the calculation, as it does not affect the final result significantly. A total rms jitter of approximately 1 ps is obtained using Eq. 3.
10k
100k
1M
10M
100M
1G
FREQUENCY OFFSET (Hz)
小碎步
PHASE NOISE (dBc/Hz)
f m
–150
RMS PHASE JITTER (radians) ≈2•10 = 6.32×10–4radians
A/10
RMS JITTER (conds) =
RMS PHASE JITTER (radians)
黄山介绍资料2 πf O
A = –150dBc + 10 log 10
200×106–0.01×106
= –150dBc + 83dB = –67dBc
= 1ps
幻想英文
Figure 5: Sample Jitter Calculation Assuming Broadband Pha Noi
Crystal oscillators generally offer the lowest possible pha noi and jitter, and some examples are shown for comparison in Figure 6. All the oscillators shown have a typical 1/f corner frequency of 20 kHz, and the pha noi therefore reprents the white pha noi level. The two Wenzel oscillators are fixed-frequency and reprent excellent performance (Reference 9). It is difficult to achieve this level of performance with variable frequency signal generators, as shown by the –150 dBc specification for a relatively high quality generator.
Wenzel ULN Series*–174dBc/Hz @ 10kHz+
Wenzel Sprinter Series,–165dBc/Hz @ 10kHz+ High Quality Signal Generator –150dBc/Hz @ 10kHz+ z Thermal noi floor of resistive source in a matched system @ +25°C = –174dBm/Hz z 0dBm = 1mW = 632mV p-p into 50Ωz * An oscillator with an output of +13dBm (2.82V p-p) into 50Ωwith a pha noi of –174dBc/Hz has a noi floor of
+13dBm –174dBc = –161dBm, 13dB above the thermal noi floor (Wenzel ULN and Sprinter Series Specifications and Pricing Ud with Permission of Wenzel Associates)
Figure 6: 100-MHz Oscillator Broadband Pha Noi Floor Comparisons (Wenzel ULN
and Sprinter Series Specifications and Pricing ud with Permission of Wenzel
Associates)
At this point, it should be noted that there is a theoretical limit to the noi floor of an oscillator determined by the thermal noi of a matched source: –174 dBm/Hz at +25°C. Therefore, an oscillator with a +13-dBm output into 50 Ω (2.82-V p-p) with a pha noi of –174 dBc/Hz has a noi floor of –174 dBc + 13 dBm = –161 dBm. This is the ca for the Wenzel ULN ries as shown in Figure 6.
Figure 7 shows the jitter calculations from the two Wenzel crystal oscillators. In each ca, the data points were taken directly for the manufacturer's data sheet. Becau of the low 1/f corner frequency, the majority of the jitter is due to the "white" pha noi area. The calculated values of 64 fs (ULN-Series) and 180 fs reprent extremely low jitter. For informational purpos, the individual jitter contributions of each area have been labeled parately. The total jitter is the root-sum-square of the individual jitter contributors.
1001k 10k 100k 1M 10M
PHASE
NOISE (dBc/Hz)
100
1k
10k
100k
1M
10M
PHASE
NOISE (dBc/Hz)
100M
100M
Figure 7: Jitter Calculations for Low Noi 100-MHz Crystal Oscillators
抖音最火的音乐(Pha Noi Data ud with Permission of Wenzel Associates)
缅甸签证In system designs requiring low jitter sampling clocks, the costs of low noi dedicated crystal oscillators is generally prohibitive. An alternative solution is to u a pha-locked-loop (PLL) in conjunction with a voltage-controlled oscillator to "clean up" a noisy system clock as shown in Figure 8. There are many good references on PLL design (e References 10-13, for example), and we will not pursue that topic further, other than to state that using a narrow bandwidth loop filter in conjunction with a voltage-controlled crystal oscillator (VCXO) typically gives the lowest pha noi. As shown in Figure 8, the PLL tends to reduce the "clo-in" pha noi while at the same time, reducing the overall pha noi floor. Further reduction in the white noi floor can be obtained by following the PLL output with an appropriate bandpass filter.
