专利名称：Clock verification
发明人：Ashish Darbari
申请号：US14674555
申请日：20150331
升级英语公开号：US09563727B2
公开日：新生儿生理性黄疸
产品快题设计20170207春雨的成语
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摘要：Methods and systems for verifying a derived clock using asrtion-bad verification. The method compris counting the number of full or half cycles of a fast clock that occur between the rising edge and the falling edge of a slow clock (i.e. during the ON pha of the slow clock); counting the number of full or half cycles of the fast
clock that occur between the falling edge and the rising edge of the slow clock (i.e. during the OFF pha of the slow clock); and verifying the counts using asrtion-bad verification.
申请人：Imagination Technologies Limited
地址：Kings Langley GB
国籍：GB
会议通知格式代理机构：Vorys, Sater, Seymour and Pea LLP
代理人：Vincent M DeLuca
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