DECISION FEEDBACK EQUALIZER

更新时间:2023-06-28 05:48:41 阅读: 评论:0

什么是社区矫正专利名称:DECISION FEEDBACK EQUALIZER
白云对发明人:Yasushi Amamiya
申请号:US14795888
对老师感谢的话申请日:20150709
正多边形定义公开号:US20150319019A1
公开日:
20151105
专利内容由知识产权出版社提供
专利附图:
摘要:A decision feedback equalizer that can operate at higher speed is provided. The decision feedback equalizer includes a weighting addition circuit (adder , coefficient units Tap, Tap to Tapn) that sums an input signal to weighted versions of feedback signals FB to FBn, n being an integer not less than 2. The decision feedback equalizer also includes a
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decision circuit that decides whether or not the result of addition by the weighting addition circuit is not less than a defined threshold value and that outputs the result of the decision to outside and to a shift register (latch circuits L to Ln). The decision circuit operates in synchronism with a clock signal. The shift register quentially holds the result of decision of the decision circuit in synchronism with the clock signal, and outputs the contents held by its component registers as feedback signals FB to FBn. The decision feedback equalizer includes a decision circuit that decides whether or not the result of addition by the weighting addition circuit is not less than a defined threshold value and that outputs the result of decision as feedback signal FB. The cond decision circuit operates in synchronism with the clock signal (FIG. ).
申请人:Renesas Electronics Corporation
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地址:Kawasaki-shi JP
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国籍:JP梦入桃花源
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