养殖土元Center for Reliable
Computing TECHNICAL NOTE
Preprint
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Chang, J. T.-Y., and E.J. McCluskey, "SHOrt Voltage Elevation (SHOVE)
Test for Weak CMOS ICs."
96-2Center for Reliable Computing
Gates 2A
(CSL TN # 96-404)Computer Systems Laboratory
Departments of Electrical Engineering and Computer Science
Stanford University
November 1996Stanford, California 94305-9020
Abstract:
This Technical Note contains a preprint of a paper submitted to the 15th IEEE VLSI Test Symposium to be held on April 27-30, 1997 at Monterey, CA.
Funding:
This work was sponsored in part by the National Science Foundation under Grant No. MIP-9107760, and by LSI Logic Corporation under Agreement No. 16517.
Copyright © 1996 by the Center for Reliable Computing, Stanford University.
All rights rerved, including the right to reproduce this report, or portions thereof, in any form.
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虚心竹有低头叶SHOrt Voltage Elevation (SHOVE) Test for Weak CMOS ICs
Jonathan T.-Y. Chang and Edward J. McCluskey
CRC-Stanford University
Room #236, MC 9020
Gates Building 2A
Stanford, CA 94305
Telephone: (415) 723-1258
FAX: (415) 725-7398
E-mail: tychang@shasta.stanford.edu
Designate contact person and prenter: Jonathan T.-Y. Chang
Topic: Test quality improvement, Intermittent failures, Early life failures, Non-traditional test.
ABSTRACT
A stress procedure for reliability screening, SHOrt Voltage Elevation (SHOVE) test, is analyzed here. During SHOVE, test vectors are run at higher-than-normal supply voltage for a short period. Functional tests and IDDQ tests are then performed at the normal voltage. This procedure is effective in screening oxide thinning, which occurs when the oxide thickness of a transistor is less th
an expected, and via defects. The stress voltage of SHOVE testing should be t such that the electrical field across an oxide is approximately 6MV/cm. The stress time can be calculated by using “effective oxide thinning” model. We will also discuss the requirement of input vectors for stressing complementary CMOS logic gates and CMOS domino logic gates efficiently.
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1. INTRODUCTION
SHOVE testing aims at screening early-life failures and intermittent failures so that we can improve the quality level of CMOS ICs at low cost. In conjunction with other testing techniques, such as IDDQ testing [Levi 81] and Very-Low-Voltage (VLV) Testing [Hao 93] [Chang 96a] [Chang 96b], we can ensure CMOS ICs’ quality without performing burn-in. During SHOVE, test ts, such as single stuck-at or pudo stuck-at test ts, are run at higher-than-normal supply voltage for a short period. Some defects occurred after SHOVE can only be detected by functional tests and some can only be detected by IDDQ tests. Thus, functional tests and IDDQ tests should be performed at normal operating voltage after SHOVE. Figure 1 shows the procedure of SHOVE testing. It has been found that IDDQ values of some CUTs increa significantly after SHOVE [Duey 93] [Jophso
n 95]. SHOVE testing is uful at wafer sort. It can screen out weak parts during a wafer-level test and remove the cost of packaging them. This procedure has been widely practiced in industry [Kowalczyk 90] [Duey 93] [Jophson 95]. Some data which showed the correlation between the effectiveness of burn-in and SHOVE testing were reported recently [Barrette 96] [Kawahara 96]. However, no detailed analysis has been found in any published literature. This paper will provide a theoretical study of SHOVE testing.
Figure 1 SHOVE testing procedure
Although burn-in can provoke various defects and improve the reliability of CMOS ICs [Hnatek 95], it increas the production cost and lengthens the test time. IDDQ testing can detect weak parts, whic
h are ICs with low mean-time-to-failure (MTTF) [McCluskey 91], by measuring their quiescent currents. On the other hand, VLV testing can make weak parts fail functional tests at very low voltage. Both IDDQ testing and VLV testing do not change the characteristics of a circuit-under-test (CUT).
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Unlike IDDQ testing and VLV testing, SHOVE testing detects weak parts by changing their intrinsic characteristics.
Oxide defects are one of the major caus for the reliability problems for CMOS ICs [Hnatek 95]. Particulate contamination, crystalline defects in the substrate, spot defects, localized thin regions, or surface roughness can cau localized weak spots in an oxide [Syrzycki 87] [Lee 88]. Moreover, the quality and lifetime of a gate oxide strongly depend on its thickness [Lee 88]. Oxide thinning occurs when the oxide thickness of a transistor is physically or effectively thinner than expected. Oxide thinning can be due to localized thin spots, traps in the oxide, surface asperity, or locally reduced tunneling barrier height [Schuegraf 94]. It can shorten the lifetime of a gate oxide, increa oxide leakage current, or cau time-dependent dielectric breakdown. As a result, it can cau early-life fa
ilures and must be detected. We investigated the device behavior during and after SHOVE. It is found that oxide thinning can cau stress-induced oxide leakage or become a gate oxide short after SHOVE and thus increa the IDDQ values of the defective CUT.
SHOVE can also make some via defects become opens, which can then be detected by either IDDQ measurements or functional tests depending on the characteristics of the resulting opens [Barrette 96] [Kawahara 96]. SHOVE, however, is less effective in stressing electromigration. Instead of using SHOVE tests, temperature stress is more effective to stress metalization becau electromigration has bigger temperature activation energy [Hnatek 95]. On the other hand, temperature stress has less effects on oxide defects becau of their low temperature activation energy [Hnatek 95].
To stress defective oxides effectively and still avoid damaging flawless oxides or causing latchup, the electrical field across the oxides, E ox, must be carefully controlled. Fowler-Nordheim tunneling currents may occur across flawless oxides if E ox is larger than a critical value. The excess tunneling currents flowing through gate oxides can damage the oxides. The damage can cau incread oxide leakage currents even after the supply voltage is reduced to the normal operating voltage. Bad on various published measurement data, the critical E ox to avoid the Fowler-Nordh
eim tunneling current is approximately 6MV/cm [Moazzami 92] [Dumin 93] [Dumin 94] [Watanabe 94] [Depas 96]. E ox at the normal operating voltage for different technologies is always well below this critical value [Schutz 94] [Charnas 95] [Sanchez 96] [Montanaro 96]. By applying the critical E ox across the flawless oxide during SHOVE, we can maximize the stress effects on the defective oxides and also minimize the stress time.
In a CMOS IC, each transistor must be stresd for enough time during SHOVE. To effectively stress an NMOS transistor, the gate of the transistor should be held at the stress voltage and the drain and source of the transistor at 0V. Similarly, to effectively stress a PMOS transistor, the gate of the transistor should be held at 0V and the drain and source of the transistor at the stress voltage. Both single stuck-at and pudo stuck-at test ts can be the stress vectors for SHOVE testing for fully
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complementary static CMOS logic. We also investigated the toggle probability of various test ts in a CUT. For pudo stuck-at test ts, some nodes were in logical one or zero for one or two vectors only. Thus, each vector must be held for at least the stress time for a transistor to make sure all tran
sistors in a CMOS IC are stresd for enough time. For domino-type dynamic CMOS logic, only an all-one vector is required to stress all the transistors within each functional block. The stress speed should be the reciprocal of the stress time for a transistor in this ca. The stress time of a transistor is the time to effectively stress an oxide.
This paper is organized as follows. Section 2 examines the behavior of oxide thinning via defects during and after SHOVE. Section 3 discuss the stress voltage. Section 4 investigates the stress vectors. Section 5 analyzes the stress time and stress speed. Section 6 concludes this paper.
2. OXIDE THINNING AND VIA DEFECTS
SHOVE testing can increa the leakage current or cau oxide breakdown in a defective oxide who thickness is less than expected. Oxide thinning shortens the lifetime of an oxide. As the oxide thickness is decread in advanced technologies [Charnas 96] [Gronowski 96] [Montanaro 96] [Sanchez 96], oxide thinning becomes a more rious problem. Furthermore, as the number of metal layers increas in most advanced technologies, via defects are more likely to occur. SHOVE testing can make some via defects become permanent opens.
Several models have been propod to predict the lifetime of an oxide and the ont criteria of oxide
breakdown. Lee et al. propod using “effective oxide thinning” to characterize time-dependent-dielectric-breakdown [Lee 88]. Sune et al. propod a statistical description of oxide breakdown bad on neutral trap generation in the oxide during wearout [Sune 90]. Dumin et al. found out that breakdown occurred locally when the local density of traps exceeded a critical value and the product of the electric field and the higher leakage currents through the traps exceeded a critical energy density [Dumin 94]. We u the “effective oxide thinning” model to estimate the lifetime of an oxide in this paper becau this model shows the relationship among the voltage across an oxide, effective oxide thickness, and oxide lifetime more directly than other models. Equation 1 shows the relationship among the parameters. X eff is the effective oxide thickness, V ox is the voltage across the oxide, t BD is the time-to-breakdown of the oxide, τ0is determined by the intrinsic breakdown time under an applied voltage of V ox, and G is the slope of log(t BD) versus 1 / E ox.
t
GX
V
BD
eff
ox
=τ
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exp()
(1)
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