Timing Constraints
Following along the forum traffic, it has come to may attention that timing constraints are often a mystery to new urs. In order to help tho who have never had to constrain their timing, I offer the following part one, of five parts, on timing constraints.
Some Basics
Timing constraints apply to nets or networks, the path or paths taken from one element to all of the inputs of subquent elements. One can also call out a specific path that is part of a net or network.
Every design should have at least one period constraint that specifies the clock and the duty cycle of the clock. A clock is always required for synchronous design, and so the period constraint is the most basic and is always a required constraint for any design. If there is more than one clock, each requires its own period constraint.
The period constraint will define how all nets must be routed in order to meet the timing requirements for proper operation.
A group may be defined to generically refer to many nets or paths of a lected t, such as a bus or c
水痘饮食ontrol group.
Priority
When it comes to having many constraints for a design the following applies: the more general the constraint, the lower its priority, and, converly, the more specific a constraint, the higher the priority.For example, a period constraint on a clock net or network is very general and will be over-ruled by a from:to constraint on a specific net or network.
The specific constraint for the from:to (or from:thru:to) is deemed more important than the more general constraint for any net within a clock domain.
There is a timing specification interaction report (the .tsi report) that details how the constraints interact. Select this option in the timing analyzer for reporting if you have a t of constraints, and you need to know how they are interacting and which priorities have been t.
One can override the assumed priorities and manually t the priority of any timing constraint. The u of the priority command allows tting a very low priority, such as 0, or even a negative priority, such as -10, which will be evaluated with an even higher priority than 0.
Example 1
The PERIOD constraint only covers nets from Synchronous Elements to Synchronous Elements, such as FFS to FFS, as shown in blue below:
NET "clk20" TNM_NET = “tnm_clk20";
TIMESPEC "TS_clk20" = PERIOD “tnm_clk20" 20 ns HIGH 50 %;
A TIMEGRP (timing group) is created called tnm_clk20 which contains all of the downstream synchronous components that net clk20 drives. All of the paths between the synchronous elements are then constrained with the timing specification TS_clk20, which specifies a 20 ns requirement from synchronous element to synchronous element and a HIGH 50% (clk20 has a 50/50 duty cycle).
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Example 2
FROM:TO constraints are ud to define a requirement for paths that go between two groups.
TIMESPEC TS_my_fromto = FROM my_from_grp TO my_to_grp 40 ns;
tells the tools that you need to ensure that data makes it from the components in the timing group ‘my_from_grp’ to ‘my_to_grp’ in 40 ns. Timing Analyzer will still calculate the clock skew from source group to destination group, but at a lower priority (if the clocks are related). Predefined groups can be ud, for example:
TIMESPEC TS_F2F = FROM FFS TO FFS 40 ns;
If we need leave out the time unit (ns, ps, etc…), then the tools presume ns:
TIMESPEC TS_P2P = FROM PADS TO PADS 30;
You can leave FROM or TO off of the constraint and make it more generic:
TIMESPEC TS_2P = TO PADS 40;
All of the FROM:TO constraints in the examples above would be of higher priority than the PERIOD constraint.
TSI Report
The TSI report is generated with the ‘-tsi design.tsi’ switch in the TRCE command line, or by specifying the option in the timing analyzer. If a ur does not e a path under the correct constraint, this is the best place to start. This report will also make suggestions on ways to一粒沙子
improve constraints in the universal constraints file (UCF). This report will also notify the ur of any paths that are constrained by multiple clock domains:
Example 3
Constraint Interaction Report
=============================流言
Constraint interactions for TS_clk0_1 = PERIOD TIMEGRP "clk0_1" TS_clk HIGH 50%;
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1 paths removed by TS_my_fromto = MAXDELAY FROM TIMEGRP "my_to_grp" TO TIMEGRP "FFS" 40 ns;
Analysis of Example 3
In other words, the FROM:TO constraint (just one) was applied ahead (higher priority) of the PERIOD constraint.
Following along the forum traffic, it has come to my attention that timing constraints are often a mystery to new urs. In order to help tho who have never had to constrain their timing, I continue with part 2 (of 5) on timing constraints.
Setup and Hold铁路货场
In a practical synchronous digital system, the data must arrive before the clock edge that samples it. The minimum amount of time in which the data must arrive before the clock edge is called the tup time.
As well as arriving before the clock edge, the data must persist for some finite amount of time at the clock edge. This is called hold time. Hold time may be negative, zero, or positive. When it is negative, the data goes away before the clock edge. When it is zero, the data persists until the clock edge. When it is positive, the data persists for some time after the clock edge.
By design, in the FPGA fabric, for all speed grades, all hold times are either negative or zero. This si
mplifies the placement and routing, as the data only needs to arrive before the clock edge, and is allowed to change immediately following a clock edge. The value that the data exceeds the minimum tup time is known as slack. Slack should always be positive. If a report shows a negative slack, then the tup timing will be inadequate (data will arrive too late).
The clock path itlf has delay, or skew. Thus, to analyze the timing, the tools will calculate the arrival time of the data and the clock at the flip-flop of interest. Constraints
If you recall from last time, the period constraint defines the clock period for the synchronous elements of interest (the flip-flops). The timing analyzer verifies that all paths between synchronous elements meet the tup and hold timing for your design. A violation of a period constraint will appear in the timing report, and have a negative slack value. It will either be identified as violating a tup requirement or a hold requirement.
If a tup requirement has been violated, then the data needs to arrive at the flip-flop sooner. To do so may require a faster path. If the place and route software cannot find a faster path, you do have the option of placing the path manually in the FPGA_Editor tool, but this is a tool of last resort. It is better to try to re-architect the circuit to meet the requirement. One way to do this is to place a flip-fl
op earlier in the path. This is known as pipe-lining, and will add latency to the signal, but it will also allow the value to be captured properly.
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If a hold requirement has been violated (the data went away before the clock edge arrived), then this is often an indication that you have a design problem (bad architecture). Values should only change on the clock edge, and not before. If an external value is changing before the clock edge, one needs to delay the clock edge (using a DCM or PLL) so that the data is now registered properly by the new delayed clock.
An alternative is to u the Idelay element in the IOB to move the data to where the clock is valid.
Data Valid Window
The time from before the clock edge (tup) plus the time after the edge (hold) is known as the data valid window, or the time the data must be stable to be properly registered. If the data is not valid for at least this amount of time, then the results are indeterminate, or unknown.
Metastability
Just becau the data was not valid for as long as required does not mean that the output of the flip-
flop is metastable--metastable is different from indeterminate! An output could be 0 or 1, emingly at random, if the timing is not met. Metastability means the edge was “almost” capable of capturing the state and the flip-flop output is in some intermediate state (not 1, not 0) for some time after the clock
edge. Metastability cannot be prevented, as it is a fact of the physics of the circuits, if the clock edge and the data are almost perfectly “misd.”
In a properly designed synchronous system there are no problems with metastability. Metastability is a problem when something is asynchronous, like pressing a key on a keyboard, or when two synchronous clocks are asynchronous to each other. When something is asynchronous, it needs to be synchronized.
For how to deal with metastability, plea consult:
www.stanford.edu/class/ee183/handouts_spr2003/synchronization_pres.pdf
Next time: Tprop, or offts.
Following along the forum traffic, it has come to may attention that timing constraints are often a mys
tery to new urs. In order to help tho who have never had to constrain their timing, I continue with part 3 (of 5 parts) on timing constraints.
Tprop or Offt
The time it takes to get a signal from point A to point B is called the propagation time. It is bad on the speed of light through a medium. For example, a trace on a printed circuit board carries signals at around 6 to 7 picoconds per millimeter. Finding this time can be done by running simulations or solving equations when you know the dielectric constant for the material and the geometry of the wiring traces. Inside the silicon device the signals behave in much the same way, but also may be delayed by going through active circuits (buffers, inverters, logic and interconnect).
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Often, you can also measure the times with the help of an oscilloscope. Propagation times generally do not vary much at all when the path has no active elements. If the path is in silicon, the strength of the transistors will cau the path delay to vary with both a maximum value and a minimum value. Timing needs to be met for both, obviously.
In order to tell the tools when data arrives at a particular location, offt constraints are ud.
OFFSET_IN
The OFFSET IN constraint defines the relationship of a clock and data as they enter the device:
OFFSET = IN 2 ns VALID 16 ns BEFORE “clk20";
