体育英文1. General Behavior Parameters
Parameter name Default Range (axSetIntParam "acts" "worst condition" 1)1[0,999999] (axSetIntParam "acts" "typical condition" 1)1[0,999999] (axSetIntParam "acts" "best condition" 1)1[0,999999] Description
The Astro clock tree synthesis (CTS) parameters have the ability to optimize skew for different operating conditions simultaneously. The three parameters can be ud to change the weight of the priority given to each condition. If an operating condition is delected in the clock tree synthesis dialog box, its weight will be t to zero irrespective of the tting in this parameter. Worst, typical, and best are the three types of operating conditions. Value 0 means no considering in this condition type, while a nonzero value means yes during clock tree synthesis. The values of the three types indicate the relative priority among the three conditions during clock tree synthesis (the higher the value, the higher the priority). Range has no special meanings. For example: worstcondition=1,typicalcondition=2,bestcondition=3 equals to
worstcondition=356,typicalconditon=567,bestcondition=987
Parameter name Default Range (axSetIntParam "acts" "delay inrtion before gate" 1)1[0,1]
Description
To understand the behavior of this parameter, you need to be aware that Astro clock tree synthesis will build the clock tree one gate level at a time. T hat is, for every clock-gating cell preexisting in the clock tree, Asto clock tree synthesis will first do a clock tree synthesis of its fanout and hook up the clock-gating cell to the next higher level subtree as appropriate. The clock-gating cells, as well as any cells that are connected to the clock tree having a sync pin but not being a register or latch, are called hookup pins. By turning this parameter off, the ur is instructing clock tree synthesis that it is not allowed to add any delay cells before a hookup pin to delay balance the buffer level driving the hookup pin; that is, all hookup pins will be connected directly to the driver of that buffer level.
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Parameter name Default Range (axSetIntParam "acts" "gated clock tree" 1)1[0,1]
Description
This parameter can be ud to turn on or off gated clock tree synthesis. If it is turned off, all cells in the fanout of the root clock net will be treated as clock sinks.
Parameter name Default Range (axSetIntParam "acts" "size up clock gates" 1)1[0,1]
Description
This parameter can be ud to preprocess the clock tree for preexisting gates in the clock tree. It is different from the clock common options dialog box tting for gate sizing. With this parameter, all gating cells in the clock tree will be sized to their largest available drive strength before any other processing is done. With the dialog box option, you enable that clock tree optimization will size the gates on an as-needed basis.
Parameter name Default Range (axSetIntParam "acts" "move clock gates" 1)1[0,1]
Description
This parameter can be ud to preprocess the clock tree for preexisting gates in the clock tree. It is different from the clock common options dialog box tting for gate relocation. With this parameter, all gating cells in the clock tree will be moved to be located at the center of their fanout before any other processing is being done. Using the dialog box option, you enable clock tree optimization to move the gates on an as-needed basis.
2. Legalization Controlling Placement Parameters
Parameter name Default Range (axSetIntParam "acts" "legalize placement" 1)1[0,1]
Description
This parameter controls whether placement legalization for cells added by clock tree synthesis is performed or not. Turning legalization off will make the switches for "OV" and "ECO placement" have no effect. Without legalization, buffers will be dropped exactly at the location deemed optimal by clock tree synthesis for clock purpo. Therefore, not performing legalization can be uful for debugging to get an upper bound on quality of results (QoR) and to parate legalization problems from other issues.
Parameter name Default Range (axSetIntParam "acts" "OV" 1)1[0,1]
Description
This parameter controls whether overlap removal is ud to legalize clock buffers added by Astro. If overlap removal is ud, every buffer will be individually immediately legalized as soon as it gets created. If overlap removal is enabled, ECO placement will be automatically disabled (e below). If "legalize placement" is turned on but overlap removal is turned off, the lock buffer locations will be ch
on to take advantage of available space but no legalization will be performed to move other cells. Parameter name Default Range (axSetIntParam "acts" "t OV maximum displacement" 2147483647)2147483647[0,99999999] Description
This parameter ts the maximum displacement during OV. The unit is um in DB.
Parameter name Default Range (axSetIntParam "acts" "ECO placement" 1)1[0,1]
Description
If this parameter is turned on, a global ECO placement will be performed after initial clock tree synthesis; that is, before embedded clock tree optimization. While this parameter is on by default, the ECO placement will not actually be performed becau the overlap removal switch is also on by default—which disables the affect of this parameter.
Parameter name Default Range (axSetIntParam "acts" "ECO weight" 2)2[0,6]
Description
Define an ECO weight that will be given to all cells connected to the clock tree (sinks, inverters, or buffers) to give preference to clock-related cells during overlap removal.
3. Effort Related Parameters
Parameter name Default Range (axSetIntParam "acts" "reclustering iterations" 4)4[0,999999] Description
This parameter ts the number of iterations the clustering algorithm will take during clock tree construction. The actual number of iterations is determined by the product of "synthesis effort" and "reclustering iterations."
Parameter name Default Range
(axSetIntParam "acts" "synthesis effort" 2)2[1,3]
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Description
This parameter is identical to the synthesis effort option in the clock common options. Setting the value in the dialog box and pressing OK will overwrite the value t by the switch, and tting the switch after using the dialog box will overwrite the dialog box. The value of This parameter will be multiplied with the reclustering iterations to come up with the number of reclustering iterations actually ud.
Parameter name Default Range
(axSetIntParam "acts" "clustering effort" 1)1[1,3]
Description
1 = low,
2 = medium,
3 = high
Low and medium effort are the same. If high effort is lected, a more involved clustering algorithm bad on pairing is invoked. This parameter is orthogonal to the reclustering iterations. For example, if effort is t to high, the high effort clustering will be executed for the number of iterations specified by reclustering iterations.
Clock Constrain Targets Parameters
Parameter name Default Range (axSetRealParam "acts" "target: clock inrtion delay" 0.000)0[0.000,999999.000] Description
This parameter is equivalent to the clock common options dialog box tting for clock inrtion delay. It will be ud as a target for the overall inrtion delay of the clock tree; that is, if the tree resulting from clock tree synthesis has a smaller inrtion delay, delay inrtion will be performed to meet the target. This target value will be overridden by a target specified through the t_clock_latency tting in the Synopsys Design Constraints (SDC) file (e below).
Parameter name Default Range (axSetRealParam "acts" "target: clock skew" 0.000)0[0.000,999999.000] Description
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This parameter is equivalent with the clock common options dialog box tting for skew target. It will be ud as a target for the overall skew of the clock tree. However, it will show an effect only if the clock tree analyzer is ud (e below). If the SDC file specifies a t_clock_uncertainty constraint, the smaller of the targets in the dialog box and the SDC file will be ud. Parameter name Default Range
(axSetRealParam "acts" "target: transition delay ri" 0.000)0[0.000,999999.000] Description
This parameter will directly be ud by clock tree synthesis when creating the tree topology. The clustering and buffer level creation will be done such that each resulting clock net has a transition tim
e "clo" to the target. This means that the actual transition time can be slightly bigger or smaller than the target. If the clock tree analyzer is ud, the target transition value will be overridden by the clock tree analyzer (e below). This ri transition target will be overridden if the ri target for best and worst are specified parately (e below).
Parameter name Default Range (axSetRealParam "acts" "target: worst transition delay ri" 0.000)0[0.000,999999.000] Description
creation will be done such that each resulting clock net has a transition time "clo" to the target. This means that the actual transition time can be slightly bigger or smaller than the target. If the clock tree analyzer is ud (e below) the target transition value will be overridden by the clock tree analyzer. This worst ri transition target will override the "target: transition delay ri"(e above for worst ca)
Parameter name Default Range (axSetRealParam "acts" "target: best transition delay ri" 0.000)0[0.000,999999.000] Description
This parameter will directly be ud by clock tree synthesis when creating the tree topology. The clustering and buffer level creation will be done such that each resulting clock net has a transition tim
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e "clo" to the target. This means that the actual transition time can be slightly bigger or smaller than the target. If the clock tree analyzer is ud (e below), the target transition value will be overridden by the clock tree analyzer. This best ri transition target will override the "target: transition delay ri" (e above).
Parameter name Default Range (axSetRealParam "acts" "target: transition delay fall" 0.000)0[0.000,999999.000] Description
This parameter will directly be ud by clock tree synthesis when creating the tree topology. The clustering and buffer level creation will be done such that each resulting clock net has a transition time "clo" to the target. This means that the actual transition time can be slightly bigger or smaller than the target. If the clock tree analyzer is ud, the target transition value will be overridden by the clock tree analyzer (e below). This fall transition target will be overridden if the fall target for best and worst are specified parately (e below).
Parameter name Default Range (axSetRealParam "acts" "target: worst transition delay fall" 0.000)0[0.000,999999.000] Description
This parameter will directly be ud by clock tree synthesis when creating the tree topology. The clus
tering and buffer level creation will be done such that each resulting clock net has a transition time "clo" to the target. This means that the actual transition time can be slightly bigger or smaller than the target. If the clock tree analyzer is ud, the target transition value will be overridden by the clock tree analyzer (e below). This worst fall transition target will override the "target: transition delay fall" (e above).
忧虑的反义词Parameter name Default Range (axSetRealParam "acts" "target: best transition delay fall" 0.000)0[0.000,999999.000] Description
This parameter will directly be ud by clock tree synthesis when creating the tree topology. The clustering and buffer level creation will be done such that each resulting clock net has a transition time "clo" to the target. This means that the actual transition time can be slightly bigger or smaller than the target. If the clock tree analyzer is ud, the target transition value will be overridden by clock tree synthesis (e below). This best fall transition target will override the "target: transition delay fall" (e above).童话故事公主
Parameter name Default Range (axSetRealParam "acts" "target: load capacitance" 0.000)0[0.000,999999.000] Description
creation will be done such that the load capacitance (wire and pin) of each clock buffer is "clo" to the target. This means that the actual load can deviate by a few units from the specified target.
Parameter name Default Range (axSetRealParam "acts" "target load relax" 0.000)0[0.000,999999.000] Description
This parameter can be ud to enable a relaxation of the the target load with each buffer level. When this parameter is t, the target load will be ud only for the leaf level of the clock tree. For all higher buffer levels u <target load actual>=<target load>*(1+<targetLoad_relax>(<buffer_level-1>))
Parameter name Default Range (axSetIntParam "acts" "target fanout" 32)32[0,999999] Description
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This parameter will directly be ud by clock tree synthesis when creating the tree topology. The clustering and buffer level creation will be done such that the fanout of each clock buffer is "clo" to the target. This means that the actual fanout can deviate by a few fanouts from the target t.
5. Clock Constraint Rules Parameters
Parameter name Default Range (axSetIntParam "acts" "rule maximum buffer levels" 20)20[0,99] Des
cription
This parameter is equivalent to the dialog box tting in the clock common options constraints sub form. It limits the level of buffers clock tree synthesis may add to value specified. It is important to understand that this constraint will be applied per gate level; that is, if your clock tree has veral rial gating cells, each subtree can have up to "rule maximum buffer levels" levels. Another thing to note is that when the maximum of levels is reached, clock tree synthesis will stop any further processing; that is, if an unrealistic constraint is specified, the resulting tree will still contain design rule checking (DRC) violations. Parameter name Default Range (axSetIntParam "acts" "rule maximum fanout" 64)64[0,999999] Description
This parameter is equivalent to the dialog box tting in the clock common options constraints sub-form. It limits the fanout each buffer in the clock tree may drive. If "rule maximum fanout" is smaller than the target fanout, the rule max fanout will be ud as target fanout (e above).
Parameter name Default Range (axSetRealParam "acts" "rule: maximum capacitance" -0.500)-0.5[0.000,999999.000] Description
