SP8400
Very Low Pha Noi Synthesir Divider
September 2005
The SP8400 is a very low pha noi programmable
divider which is bad on a divide by 8/9 dual modulus prescaler and a 12 stage control counter. This gives a minimum division ratio of 56 (64 for fractional - N synthesis applications), and a maximum division ratio of 4103. Special circuit techniques have been ud to reduce the pha noi considerably below that produced by standard dividers.The data inputs are CMOS or TTL compatible.儿童歌曲小兔子乖乖
The SP8400 is packaged in a 28 pin plastic SO package.
FEATURES
I Very low Pha Noi (Typically -156dBc/Hz at 1kHz
offt)
I Supply Voltage 5V一月份英语
ABSOLUTE MAXIMUM RATINGS
Supply Voltage 6.5V Output Current
20mA
Storage Temperature Range -55°C to +125°C
Maximum Clock Input Voltage
2.5V p-p
愿无岁月可回头Ordering Information
SP8400/KG/MPES 28 Pin SOIC Tubes SP8400/KG/MPFP
28 Pin SOIC*
Tubes
*Pb Free Matte Tin
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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
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Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Rerved.
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SP8400
ELECTRICAL CHARACTERISTICS
Guaranteed over: Supply voltage V CC = +4.75V to +5.25V Temperature T amb = -10°C to +75°C Tested at +4.75V and +5.25V at T amb = +25°C
Min.
Typ.Max.Supply current
Output voltage swing
Input nsitivity 200MHz to 1.5GHz
Data Inputs
Logic high voltage Low low voltage Input current
137410
152
140(-4)
0.8180
122320
2.2
4, 11, 12, 1820, 21
7, 8
Output loaded with 300R See Fig.4p-p @ 1.5GHz input ÷ 71 mode See Fig.4
RMS Sine wave into 50 Ohms (dBm equivalent) See Fig.3
5V Data input voltage
mA mV mV dBm V V µA
Units
Value Conditions
Characteristic
Pin
3
SP8400
APPLICATIONS INFORMATION
Circuit description, synthesir divider
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The divider is bad on a divide by 8/9 modulus prescaler, and a 12 stage control counter. This gives minimum fractional – N division ratio of 64 (56 for general division), and a maximum division ratio of 4103. The inputs to the control counter are TTL/CMOS compatible. There is a fixed offt of 8 between the number on the data lines and the actual division ratio.
中华上下五千年简介The output is one transition only per divide cycle. This eliminates the problem of where to put the redundant edge when the divider is ud in a fractional–N system, and also avoids the problem of how to define the output pul width.This means that the overall division ratio conventionally de-fined in terms of the rate of edges of the same polarity is twice the lected division ratio.
传承非遗文化Fig.4 Test circuit
Equations for division
The M and A data inputs form a 12 bit number with A0being the least significant bit and M8 being the most significant bit.
Definition 1:Division ratio – (input frequency to out
put edges, positive or negative).
= Number loaded + 8
Definition 2:
Division ratio – (input frequency to out put frequency).
= (Number loaded + 8) x 2
SP8400
Available division ratio
All division ratios of 64 to 4103 (Definition 1) will return the divider to the same internal state at the end of the count and hence the are the only divisional ratios to be ud for fractional–N synthesir application.
All division ratios of 56 to 4103 are available for general division purpos. Additional division ratios available for general division are:-
张大伟个人简历8,9
16, 17, 18
24, 25, 26, 27
32, 33, 34, 35, 36
40, 41, 42, 43, 44, 45
48, 49, 50, 51, 52, 53, 54
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