SPI Master Core Specification
Author: Simon Srot
simons@opencores
Rev. 0.6
March 15, 2004
Revision History Rev. Date Author Description
0.1 June 13, 2002 Simon Srot First Draft
珍惜时间的名言名句0.2 July 12, 2002 Simon Srot Document is lectured.
Simon Srot Support for 64 bit character len added.
0.3 December 28,
2002
Simon Srot Automatic slave lect signal generation added.
0.4 March 26,
2003
0.5 April 15 2003 Simon Srot Support for 128 bit character len added.
世界文化的特点
0.6 March 15,
Simon Srot Bit fields in CTRL changed.
2004
II INTRODUCTION. (1)
IO PORTS (2)
2.1 WISHBONE INTERFACE SIGNALS (2)
2.2 SPI EXTERNAL CONNECTIONS (2)
REGISTERS (3)
3.1 C ORE R EGISTERS LIST (3)
百年乐3.2 D ATA RECEIVE REGISTER LOW/HIGH[R X L/R X H] (3)
产妇可以吃螃蟹吗3.3 D ATA TRANSMIT REGISTER LOW/HIGH[T X L/T X H] (4)
3.4 C ONTROL AND STATUS REGISTER [CTRL] (4)
3.5 D IVIDER REGISTER [DIVIDER] (5)
3.6 S LAVE SELECT REGISTER [SS] (5)听课评语和建议
OPERATION (7)
4.1 WISHBONE INTERFACE (7)
4.2 S ERIAL INTERFACE (7)
ARCHITECTURE (9)
CORE CONFIGURATION (10)
Introduction
This document provides specifications for the SPI (Serial Peripheral Interface) Master core. Synchronous rial interfaces are widely ud to provide economical board-level interfaces between different devices such as microcontrollers, DACs, ADCs and other. Although there is no single standard for a synchronous rial bus, there are industry-wide accepted guidelines bad on two most popular implementations:
SPI (a trademark of Motorola Semiconductor)
Microwire/Plus (a trademark of National Semiconductor)
Many IC manufacturers produce components that are compatible with SPI and Microwire/Plus.
The SPI Master core is compatible with both above-mentioned protocols as master with some additional functionality. At the hosts side, the core acts like a WISHBONE compliant slave device.
Features:
优美的词
Full duplex synchronous rial data transfer
Variable length of transfer word up to 128 bits
MSB or LSB first data transfer
报表管理Rx and Tx on both rising or falling edge of rial clock independently
8 slave lect lines
Fully static synchronous design with one clock domain
Technology independent Verilog
Fully synthesizable
IO ports 2.1 WISHBONE interface signals
Port Width Direction Description
wb_clk_i 1 Input Master clock
wb_rst_i 1 Input Synchronous ret, active high
wb_adr_i 5 Input Lower address bits
wb_dat_i 32 Input Data towards the core
wb_dat_o 32 Output Data from the core
wb_l_i 4 Input Byte lect signals
wb_we_i 1 Input Write enable input
wb_stb_i 1 Input Strobe signal/Core lect input
wb_cyc_i 1 Input Valid bus cycle input
wb_ack_o 1 Output Bus cycle acknowledge output
wb_err_o 1 Output Bus cycle error output
wb_int_o 1 Output Interrupt signal output
Table 1: Wishbone interface signals
All output WISHBONE signals are registered and driven on the rising edge of wb_clk_i. All input WISHBONE signals are latched on the rising edge of wb_clk_i. 2.2 SPI external connections
虚的成语Port Width Direction Description
/ss_pad_o 8 Output Slave lect output signals
sclk_pad_o 1 Output Serial clock output
mosi_pad_o 1 Output Master out slave in data signal output
miso_pad_i 1 Input Master in slave out data signal input
Table 2: SPI external connections
