AD9361
影字组词
RF and BB PLL Synthesizer
Ur Guide
Rev 2.4.立秋时间
Information furnished by Analog Devic es is believed to be ac c urate and reliable. However, no
responsibility is assumed by Analog Devices for its u, nor for any infringements of patents or other rights of third parties that may result from its u. Specifications subject to change without notice. No One Tec hnology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
GENERAL DESCRIPTION
The AD9361 transceiver contains two identical RFPLL synthesizers to generate the required LO signals. One is programmed for the RX channel and the other for the TX channel. The transceiver also contains a BBPLL synthesizer to generate the required sampling and internal operational clocks. The PLL synthesizers are all of fractional–N architecture with completely integrated VCOs and loop filters. They require no external parts to cover the entire frequency range of the device. This configuration allows the u of any convenient reference frequency for operation on any channel with any sample rate. For FDD operation, the frequency of TX and RX can be different and both RFPLL synthesizers operate simultaneously. For TDD operation, the RFPLL synthesizers alternately turn on as appropriate for RX and TX frames.
REVISION HISTORY
3/11—1.0 Distribution
4/11—1.1 Edit formatting add table. Applies to R1 version.
6/11—2.0 Update fixed writes for R2. Add Fast Lock info, Ext LO.
9/11—2.1 Include FDD and TDD tables for R2. Add BBPLL ction. Examples updated.
10/11—2.2 Fixed typos.
"1万元创业项目"
11/11—2.3 Clarified BBPLL loop filter table value usage
1/12—2.4 Added how to generate TDD script with FDD calibrations to TDD MODE – Faster Lock Times ction.
General Description (2)
Revision History (2)
RFPLL Introduction (4)
AD9361 PLL Architecture (5)
Reference Block (including Reference Scalers) (5)
钓黑鱼
DCXO (6)
Main PLL Block (6)
VCO Divider Block (7)
Calculating RFPLL Divider Values (7)
Carrier Frequency tup (7)
RX (or TX) VCO Divider (7)
Charge Pump Current (9)
RFPLL Loop Filter (10)
VCO Configuration (10)
Lock Detector (11)
Synthesizer Look Up Table (11)
Example Programming Sequence (26)
TDD MODE – Faster Lock Times (28)
Frequency Correction Words (29)
FastLock Mode (30)
FastLock Initial Wider-BW Option (30)
Configuring and Using a Fast Lock Profile – Internal Registers (31)产品组合
Configuring and Using a Fast Lock Profile – EXAMPLE (34)
External LO (37)
Baband PLL (BBPLL) (39)
BBPLL VCO (39)
Calculating BBPLL Divider Values (40)
BB PLL Charge Pump (41)
BBPLL Loop Filter Values (41)
汉城湖公园BBPLL Typical Loop Filter and Charge Pump Configuration (44)
APPENDIX: RFPLL Loop Filter (45)
The AD9361 contains two identical RFPLL Synthesizers, one for RX and the other for TX, which are programmed independently. The two VCOs and loop filters are integrated on chip and have no external components. The fundamental frequency of the PLLs is from 6-12GHz. Local Oscillator frequencies ranging from 47MHz to 6GHz are created by dividing the PLL frequency.毫不示弱的意思
There are 6 areas of each PLL that will be configured for a given frequency of operation. The are:
• Reference Scaler
• PLL divider (N INT and N FRAC ) (register bits) • VCO divider (register bits) • Charge Pump (register bits)
• Loop Filter components (register bits) • VCO tuning (lf-calibration procedure)
TX2A TX1A RADIO
TX2B
TX1B SPI Port
JESD207/LVDS JESD207/LVDS
Figure 1. AD9361 Block Diagram. RX and TX synthesizers operate independently.
The synthesizers have identical but independent register ts in the device address space. Each synthesizer must be configured and calibrated parately.
ADI provides Lookup Tables for synthesizer configuration bad upon the desired reference frequency to be ud. Each lookup table covers a specific reference clock input frequency and application (FDD or TDD). A particular lookup table is indexed by the VCO frequency. At that index, the configuration data in the table cells is retrieved, then it is formatted and stored into the appropriate registers. At power up, a few registers are programmed that will typically remain the same during normal operation. At this point, a
particular table is referenced to configure the VCO and loop filter ttings for best performance over temperature. The tables provided by ADI include a column of VCO gains for different frequency ttings so that urs can customize their own loop filter if desired.
The following ctions show block diagrams of the AD9361 PLL that consist of the Reference Block, the main PLL Block, and the LO GEN Output Block. The VCO always operates between 6 to 12 GHz. Highlighted text indicates programmable items.
REFERENCE BLOCK (including Reference Scalers)
The reference frequency can be generated via the on-chip DCXO or an external clock source can provide this input to the device. If an external source is ud, a 1.3Vpp clipped sinewave would be applied to the device XTAL_N input (with XTAL_P input OPEN). A MUX lects the desired source. The reference is then split and applied to 3 independent conditioning blocks also known as scalers (or Ref Dividers in the Register Map). The conditioning blocks provide 4 options such that the PLL reference frequency F REF (the loop reference applied to the PLL pha detector) is either buffered, doubled, halved, or divided by 4. Independent blocks make it possible to have a different F REF for each PLL if desired. For best RFPLL performance, ADI recommends lecting the reference scaler that will result in a reference frequency as high as possible with the result between 35MHz and 80 MHz after scaling. Also, the same scaler configuration should be ud for both RX and TX PLLs so that the noi spectrums match. The same block functionality is provided for the BBPLL (e BBPLL ction). For best BBPLL performance, the reference scaler would be configured to result in reference frequencies between 35 and 70MHz. See Table 1 for configuration information.
Figure 2. Independent Reference Block for each PLL applies either Buffered, 2X, ½X, or ¼X Reference Frequency
For best performance, Valid F REF for TX and RX is 35-80MHz NOTE: Apply External Reference to the XTAL_N pin (XTAL_P OPEN ) (DO NOT APPLY TO REF_CLK_IN pin). See DCXO document.
Table 1 Reference Block Scaler Configuration
REF _ C LK _
I N DO NOT USE
F R EF
F R EF 80 M Hz
F R EF 80 M Hz FOR BEST PERFORMANCE: 35-70 MHz
三个火枪手2
FOR BEST PERFORMANCE: 35-80MHz
CONNECT H6 TO GROUND
