VHDL——分频器设计
1.简介
1.在数字电路设计的过程中，常常需要对较⾼频率的时钟信号进⾏分频操作，从⽽得到较低频率的时钟信号。
⼀个硬件电路，如果时钟信号设计的不对，将会导致整个硬件电路设计的失败。
2.分频器：完成对时钟信号的2分频，4分频，8分频和16分频
2.分频器设计
library ieee;
u ieee.std_logic_1164.all;
u ieee.std_logic_arith.all;
u ieee.std_logic_unsigned.all;
entity clk_2468 is
port(clk : in std_logic;
clk_div2,clk_div4,clk_div8,clk_div16 : out std_logic);
end clk_2468;
architecture behave of clk_2468 is
signal count :std_logic_vector(3 downto 0);
begin
process(clk)
begin
if(clk'event and clk = '1') then
if(count ="1111") then
count <=(others =>'0');
蛋糕8寸el
三生三世歌词count <= count +1;
end if;
end if;
end process;
clk_div2 <=count(0);
clk_div4 <=count(1);
clk_div8 <=count(2);
clk_div16<=count(3);
end behave;
3.偶数倍分频器（8分频）
library ieee;
u ieee.std_logic_1164.all;
entity divider_8 is
port(clk : in std_logic;
oul : out std_logic);
end divider_8;
architecture behave of divider_8 is
constant n : integer :=3;
signal counter : integer range 0 to n;
signal s1 : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then --严格的上升沿
付出的爱if counter = n then
counter <=0;--每四个上升沿，counter就清零 s1 <= not s1;--s1就反转（0与1）
el
counter <= counter +1;
end if;
end if;
end process;
oul <= s1;
end behave;
4.占空⽐为1:15的16分频器
library ieee;
u ieee.std_logic_1164.all;
entity div1_15 is
port(clk : in std_logic;
clk_div16 : out std_logic);
end div1_15;
architecture behave of div1_15 is
signal count :std_logic_vector(3 downto 0);
begin
process(clk)
舍什么逐什么成语begin
if(clk'event and clk = '1') then
if(count ="1111") then
clk_div16 <='1';
el
clk_div16 <='0';
end if;
end if;
end process;
end behave;
5.奇数倍分频器（3分频）
春叶流亭library ieee;
u ieee.std_logic_1164.all;
entity divider_3 is
port(clock : in std_logic;
clk : out std_logic);
角质膜
天比高end divider_3;
architecture behave of divider_3 is
constant n : integer :=2;
signal counter : integer range 0 to n; signal temp1 : std_logic;
signal temp2 : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if counter = n then
counter <=0;
temp1 <= not temp1;
el
counter <= counter +1;
end if;
end if;
if falling_edge(clock) then
if counter =2 then
temp2 <= not temp2;
end if;
end if;
end process;英语单词表
clk <= temp1 xor temp2;
end behave;
