DRC format for stacked CMOS design

更新时间:2023-06-18 22:06:06 阅读: 评论:0

专利名称:DRC format for stacked CMOS design客中初夏司马光
发明人:Yao-Jen Chuang,Nien-Yu Tsai,Wen-Ju Yang关于人的好句
申请号:US14058478
申请日:20131021
公开号:US09038010B2
公开日:
复工复产20150519寻宝路
专利内容由知识产权出版社提供
专利附图:
雪花姐姐
摘要:The prent disclosure relates a method of performing a design rule checking (DRC) procedure on a multi-tiered integrated chip. In some embodiments, the method is performed by defining layer databas for a plurality of tiers within a multi-tiered integrated chip. The layer databas respectively identify design layers within an
鲜海参的做法
associated tier. A DRC (design rule checking) deck is then generated, which defines one or more individual design layer definitions as a function of a plurality of layer databas, so that the one or more individual design layer definitions are defined for a plurality of tiers. One or more design rules for the one or more individual design layer definitions are defined within the DRC deck. Since the individual design layer definitions are defined as functions of the plurality of layer databas, the design rules apply to the plurality of tiers.
申请人:Taiwan Semiconductor Manufacturing Co., Ltd.
地址:Hsin-Chu TW
国籍:TW
仁祖代理机构:Eschweiler & Associates, LLC
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