A PROGRAMMABLE PRE-CURSOR ISI EQUALIZATION CIRCUIT FOR HIGH-SPEED
SERIAL LINK OVER HIGHLY LOSSY BACKPLANE CHANNEL Bo Wang1, Dianyong Chen1, Bangli Liang1, Jinguang Jiang2 and Tad Kwasniewski1
1DOE, Carleton University, 1125 Colonel By Dr., Ottawa, ON, K1S 5B6, Canada
2ISS, Wuhan University, Wuhan, Hubei, China 430079
ABSTRACT
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This paper prents a programmable pre-cursor ISI equalization circuit for high-speed rial data transmission over highly lossy electrical backplane channels. Although decision-feedback-equalizer (DFE) provides an effective way to compensate various channel impairments, such as frequency dependent loss, dispersion and reflections in the legacy backplane environment, for high-speed, highly lossy band-limited channel, the pre-cursor inter-symbol interference (ISI) is still a significant problem for channel equalization. A programmable pre-cursor ISI equalizer combined with a 3-tap DFE is implemented to work at 10-Gb/s and compensate the channel loss of -20 dB. The results show it outperform a traditional 5-tap DFE.
Index Terms—Backplane, ISI, equalization, decision-feedback equalizer (DFE), band-limited channel, rial link, SerDes, wireline transceiver.
1. INTRODUCTION
The continuous improvement on the performance of CMOS ICs made it possible to transmit signals at the data rates above multi-Gb/s over cables or backplanes. Due to the price-competitiveness of the legacy backplane, it is still one of the main transmission media for high-speed rial communications. The backplane is a complex environment consisting of at least 11 different components and prents a rious challenge to data rates above 5-Gb/s [2]. The multi-Gb/s data rates rial communications are running into the bandwidth limitation of the backplanes. The bandwidth limitation is mainly caud by dielectric loss, skin effect, and impedance discontinuities of the media. At data rates above the bandwidth of the band-limited channels, the received signals are verely distorted due to the inter-symbol interference (ISI).
Equalization is one of the means to compensate the distortion caud by the effects of the band-limited transmission media. The equalizer can be implemented as pre-emphasis (or de-emphasis) in the transmitter, or decision-feedback equalizer (DFE) in the receiver. There are veral categories of
equalizers ud extensively, linear or non-linear equalizers, continuous-time or discrete-time equalizers, etc. Among all the types of equalizers, DFE is the most effective one and it is regarded as the sub-optimum receiver without any decision delay [8]. Compared with the pre-emphasis in the transmitter, the DFE can be implemented with adaptation algorithms to compensate the time variation and piece-wi variation of the transmission properties of the backplane channels without extra back-channel transmission as in adaptive pre-emphasis.
Although the adaptive DFE has advantages over other equalization methods, it can not remove the pre-cursor ISI. The reason is that DFE is a strictly causal system or it removes ISI on the basis of decisions that have been made (the past bits). Therefore, the DFE performance heavily depends on the joint channel pul respon. The joint channel pul respon can be reshaped with linear equalizers. Becau the properties of a backplane channel are time variant and piecewi variant, the linear equalizers ud to reshape the joint channel pul respon should be programmable. This paper describes a programmable pre-cursor ISI equalization method for 10-Gb/s transmission over a backplane channel with –20 dB loss at Nyquist frequency. This equalizer, combined with a 3-tap DFE, has better performance than a 5-tap traditional DFE.
The next ction discuss the general properties of the backplane channels. A brief review of some
widely ud equalization structures is also given. In Section 3, the propod pre-cursor ISI equalization circuit and DFE circuits are prented. Results on this equalizer are compared with the results on a 5-tap traditional DFE are followed in Section 5. Conclusion is drawn in Section 5.
2. BACKPLANE CHANNEL AND EQUALIZATION 2.1 Backplane Channel Characteristic s
The magnitude and pha frequency respon of a typical backplane channel is shown in Fig. 1. The attenuation is about -20 dB at the 5-GHz (Nyquist frequency for 10-Gb/s data rates). The 3-dB bandwidth of this backplane is 500-MHz. The pha respon is shown in wrapped mode to 5-GHz frequency, the nearly linear pha respon can be obrved, and the delay at 5-GHz is 5.43-ns. Therefore, the distortion of the received signals is mainly from the frequency dependent loss of the channel. The notch around
泡沫大战4-GHz is caud by the impedance discontinuities and this results in reflection that deteriorates ISI in the receiver.
backplane channel (S21).
The channel pul respon when a 1-V 100-ps rectangular pul is applied to the input is shown in Fig. 2. The received pul is attenuated in magnitude, extended in time and delayed by ~5.45-ns. The pre-cursor ISI (83.33-mV) is comparable to the cond post-cursor ISI (92.06-mV). Therefore, for this channel, the DFE with as many taps as possible to completely remove post-cursor ISI can not achieve the same performance of a 3-tap DFE when pre-cursor ISI is not removed. For this channel with the pre-cursor ISI, the maximum received signal eye height that a conventional DFE can achieve is the distance from the main tap to the pre-cursor tap (315.4mV – 83.33mV = ~232mV).
The characteristics of a differential backplane channel are usually reprented by 4-port S parameters, as shown in Fig. 3. S21 is the inrtion loss, S22 is the return loss, S23 is the far-end cross-talk (FEXT), and S24 is the near-end cross-talk (NEXT). The maximum return loss of -10dB is due to the impedance discontinuities of the backplane environment.
2.2 Channel Equalization
The equalization is one of the effective means to compensate the impairments caud by the low-cost backplane environment. It can be implemented with different structures.
Pre-emphasis (also called feed-forward equalizer) is usually a multi-tap FIR filter implemented in the transmitter. Constrained by the peak transmitter power, it actually de-emphasizes the low frequency components to achieve a respon who Discrete Fourier Transform is flat. Therefore, the de-emphasis FIR reduces the ISI at the expen of received signal swing, and the signal-to-noi ratio (SNR) in the receiver is decread. Another disadvantage of the equalizer in the transmitter is the difficulty to u adaptive algorithm without a back-channel. For high-speed multi-Gb/s data transmission, it becomes more and more difficult to implement receiver equalizer in the format of FIR filter except for DFE, becau it must perform delaying, multiplying, and adding analog (or multi-level)
美丽的四季作文 signals in only one bit period (the baud period). Therefore, some continuous-time equalizer utilizes inductors or/and capacitors to obtain zeros at high frequency to flatten frequency respon. It can be implemented with on-chip inductors. Conventional design of this type of equalizer does not provide any programmability to modify the inductance or/and capacitance.
Although the feedback branch of DFE is also FIR filter, its inputs are binary. This advantage greatly simplifies circuit implementation at high data rates. In addition DFE theoretically does not enhance noi as linear equalizers do. The filter coefficients of the DFE can be adapted easily with a sign-sign least-mean-square (SS-LMS) algorithm. The tap coefficients are adapted with equation 1.
[][])(sgn )(sgn 2)()1(n d n e n C n C μ+=+ (1)
where, C(n+1) is new coefficient value, C(n) is prent coefficient value, μ is the convergence factor, e(n) is the error signal, d(n) is the received data signal and sgn[] is sign function.
Despite the various advantages of DFE it does not necessarily outperform other equalization methods for a channel with strong pre-cursor ISI. To achieve the best performance, a conventional equalizer is usually ud as a feed-forward-equalizer (FFE) to reduce pre-cursor ISI, and DFE is ud to remove post-cursor ISI. Unfortunately, it has been reported the combination of transmitter FFE and DFE only damages the link performance for highly distorted channels [3]. The combination of receiver FFE and DFE may help. However, if the FFE does not provide any programmability, it may reshape the channel respon to give more pre-cursor ISI when the channel properties vary.
3. PROPOSED PRE-CURSOR ISI EQUALIZATION
3.1 Equalization Architectures
There are veral high-speed equalization architectures published recently. A parallel-path equalizing filter with inductors and adaptive current source circuit is propod for 40-Gb/s copper cable with -10dB loss [4]. The equalizer is designed with 10 on-chip inductors. Another Rx equalizer is a 4-stage equalizer for 6-Gb/s and each RxEQ unit in one stage can compensate 5-dB at 3-GHz (
Nyquist frequency) with 4-bit programmability [5]. The equalizers are merely linear continuous-time equalization methods in the receiver side. In paper [1], a 4-tap transmitter FFE and 5-tap receiver DFE are designed to work at 10-Gb/s. However, as discusd in paper [3], transmitter FFE reduces SNR of the received signals, and it interacts with DFE adaptation. This topology only deteriorates link performance. Therefore, this paper locates the optimum sampling instants to reduce pre-cursor ISI and u unrolling DFE to eliminate post-cursor ISI.
We propod a continuous-time pre-cursor ISI linear equalization (prLE) circuit for highly lossy backplane channel in this paper. It is compod of 4-bit programmable capacitive degeneration, and two optional on-chip spiral inductors. The circuit is shown in Fig. 4. The on-chip inductors and capacitors generate two zeros above the bandwidth of the channel to amplify the attenuated high frequency signals and boost the effective bandwidth. Therefore, the pre-cursor ISI can be reduced. The inductors can be optionally bypasd for some type of channel with low loss.
The voltage transfer function of the continuous-time prLE is
()()()
()D L S S m m
IN OUT V sL R C R g g s V V s A +⋅+==/1||1 (2)
where, g m is the transconductance of NMOS MN1/MN2.
Fig. 4. The pre-cursor ISI linear equalization (prLE) circuit.
The source degeneration capacitor C S is programmable with four control bits.
∑==4
1
i Si i S C b C
(3)
The DC gain of the prLE is determined by the load resistance R L and source degeneration resistance R S .
S
L DC
V
R R A =
(4)
At frequency above the channel bandwidth, the two zeros from the load inductors and source capacitor would enhance the gain of the prLE. With g m *(Rs || /sCs) >> 1, the gain is
()()()S
S S D L V R C sR sL R s A ++=
1
(5)
3.2 Equalizer with prLE and 3-tap DFE
It can be en from Fig. 8 that the prLE not only reduces the pre-cursor ISI, but also makes the post-cursor ISI smaller. In this work, the equalization scheme combines in the receiver side a prLE for pr
e-cursor ISI reduction and a 3-tap DFE for post-cursor ISI removal. There are trade-offs in the design. The prLE is not ud to compensate all the channel loss in the whole pass-band, but to boost the channel bandwidth to reduce pre-cursor ISI. If the gain of the prLE is too large, it will also amplify much of the noi and crosstalk at frequencies where SNR is poor. The prLE can be programmed to cope with time variant channel and piece-wi variant channel.
A sign-sign LMS adaptive DFE follows the prLE is ud to remove post-cursor ISI. For the highly lossy backplane channel without prLE, the height of the eye-opening can not be improved even with 5 or more taps DFE. This is becau the pre-cursor ISI would be the dominant interference. With prL
E in the receiver to compensate the channel bandwidth, both the pre-cursor ISI and post-cursor ISI can be reduced. Therefore, the adaptive DFE can be implemented with 3-tap in this architecture. The entire equalization circuit in the receiver is shown in Fig. 5.
Fig. 5. The equalization circuit in the receiver.
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The magnitude and pha frequency respon of the prLE is shown in Fig. 6. With the two zeros, the gain is boosted for 3-dB at 500-MHz for this high loss channel, and about 14-dB at 5-GHz (the Nyquist frequency). From the pha respon, the two zeros also introduce pha distortion, but it is neglectable in the systems. The decrea of the magnitude above is due to the CMOS technology.
equalizer.
The frequency respon of the channel, the prLE and the channel+prLE is shown in Fig. 7. The bandwidth of the channel is extended to around 2-GHz with the 4-bit programmable prLE.
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combination.
4. EXPERIMENT RESULTS
The equalizer with prLE and 3-tap DFE (EUQ2) is compared with the equalizer with 5-tap DFE (EQU1).
4.1 Impul Respon
The 1-V 100-ps square impul respon of the EQU1 and EUQ2 is shown in Fig. 8. For the EQU1 (up) with 5-tap DFE, the five post ISIs are cancelled at the sampling points (the circles in the plot, and the pre-cursor one is not changed which is almost 1/3 of the main tap and clo to the 2nd post ISI in magnitude. However, the pre ISI of the EQU1 is 1/5 of the main tap, and the post 3 ISIs are cancelled with the 3-tap DFE. tap DFE and 5-tap DFE.
The comparison of the impul respon between EQU1 and EQU2 is summarized in Table1. The main tap, 1st pre-cursor ISI, and 5 post-cursor ISIs are compared. The main tap of EQU2 (prLE+3-tap DFE) is almost 3 times larger than the EQU1 (5-tap DFE), for the gain of the prLE at high
frequency. The pre-cursor ISI is 26.4% of the main tap for EUQ1, and 15.4% for EUQ2. The 3rd post-cursor ISI is lower than the first pre-cursor ISI; therefore, 3-tap DFE for post-ISI cancellation is adequate.
Table 1: Comparison of impul respon with and
without pre-cursor ISI equalization (prLE)
w/o prLE w/ prLE
Pre-cursor ISI 1 83.33mV 139.7mV
Main tap 315.4mV 906.6mV
Post-cursor ISI 1 215.5mV 169.3mV
Post-cursor ISI 2 92.06mV -196.3mV
Post-cursor ISI 3 49.46mV -115.6mV
Post-cursor ISI 4 32.92mV -23.07mV
Post-cursor ISI 5 30.38mV 11.11mV
4.2. Eye Diagram
The propod equalization system is designed for 10-Gb/s data rate over the highly lossy backplane channel (-20dB loss at 5-GHz). The eye diagram of 5-tap DFE and 3-tap DFE with prLE are compared and shown in Fig. 9. As shown in Fig 9, the received signal (a) is verely distorted due to the frequency-dependent loss of the channel; (b) the equalized signal with only 5-tap DFE, the vertical height of the eye is 165.8-mV. This is becau the pre-cursor ISI is 83.33-mV which is comparable with the 2nd post-cursor ISI. The eye-opening can not be improved with even more taps on the DFE; (c) the signal is equalized with prLE. The eye is opened, however the signal to noi ratio is not improved too much; (d) the signal is compensated with prLE and 3-tap DFE. The height of the eye is 558.6-mV which is enhanced about three times than the 5-tap DFE equalization method.
The vertical height and horizontal jitter of the eye diagram for the architecture with 5-tap DFE and with prLE + 3-tap DFE are compared and shown in Table 2.
Table 2: Comparison of eye diagram of the two
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architectures at 10-Gb/s.
Vertical height Horizontal Jitter
DFE w/o prLE 165.83mV 29.65ps DFE w/ prLE 558.60mV 27.60ps
5-tap DFE without prLE, (c) signals after prLE, and (d) equalizer with prLE and 3-tap DFE.
The vertical heights of the received signals at the data center sampling point (the dot line in Fig. 9) are compared, as shown in Fig.10. From the plot, we can e the received signals (a) are spread between 0-V and 1-V, and it is difficult to detect the high or low logic levels from the distorted signals. From the histogram plot of 5-tap DFE in Fig. 10(b), the center distributions of the low or high levels are 0.1-V or 0.5-V, respectively. The magnitude and the eye opening of the received signals are improved with prLE and 3-tap DFE equalization scheme, as shown in Fig. 10(b). Now, the distribution centers of the low and high levels are 0.1-V and 1.0-V, respectively.
tap DFE without prLE, (c) signals after prLE, and (d) equalizer with prLE and 3-tap DFE.
The horizontal jitters of the received signals with the two equalization architectures (5-tap DFE and prLE + 3-tap DFE) are compared and shown in Fig. 11. There is a little improvement on the jitter performance with the pre-cursor ISI linear equalization (prLE) in the receiver.
5. CONCLUSION
The bandwidth of the transmission media and the data rates of signals transmission conflict with each other. The inter-symbol interference (ISI) is vere when the Nyquist frequency of the transmitted signals is more above the bandwidth of the channel. To transmit signals at high speed an
d make the bandwidth ud efficiently, the pre-coding (to lower the signals bandwidth requirement) or equalization (to compensate the channel bandwidth) is extensively utilized in modern rial data communications. Decision-feedback equalizer (DFE) is still the very effective equalization method for cancelling the post-cursor ISI with adaptive algorithms. In this paper, DFE combined with a programmable pre-cursor ISI equalization (prLE) can achieve larger eye-opening (higher SNR and lower BER) with better trade-off on noi amplification and pre-cursor ISI reduction.
6. REFERENCES
[1]John F. Bulzacchelli, Mounir Meghelli, Sergey V.
Rylov, et al., “A 10Gb/s 5-tap DFE/4-tap FFE Transceiver in 90-nm CMOS technology”, IEEE J.
Solid-State Circuits, vol. 41, no. 12, pp. 2885-2900, Dec. 2006.
[2]Jared L. Zerbe, Carl W. Werner, Vladimir Stojanovic,
et al., “Equalization and clock recovery for a 2.5-10-
Gb/s 2-PAM/4-PAM backplane transceiver cell”, IEEE
J. Solid-State Circuits, vol. 38, no. 12, pp. 2121-2130,
Dec. 2003.
[3]Jihong Ren, et al., “Precursor ISI reduction in high-
speed I/O”, IEEE Symposium on VLIS Circuits, pp.
134-135, 2007.
[4]Chih-Fan Liao and Shen-Iuan Liu, “A 40Gb/s CMOS红梅什么时候开花
rial-link receiver with adaptive equalization and
CDR”, ISSCC Dig. Tech. Papers, pp. 100-101, Feb.
2008.
[5]H. Uchiki, Y. Ota, M. Tani, et al., “A 6Gb/s RX
equalizer adapted using direct measurement of he equalizer output amplitude”, ISSCC Dig. Tech. Papers,
pp. 104-105, Feb. 2008.
[6]Timothy O. Dickson, and Sorin P. Voinigescu, et al.,
“Low-power circuits for a 2.5V, 10.7-to-86-Gb/s rial
transmitter in 130-nm SiGe BiCMOS”, IEEE J. Solid-
State Circuits, vol. 42, no. 10, pp. 2077-2085, Oct.
2007.
[7]Kannan Krishna, David A. Yokoyama-Martin, Aaron
Caffee, et al., “A multigigabit backplane transceiver core in 0.13-um CMOS with a power-efficient equalization architecture”, IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2658-2666, Dec. 2005.
[8]Troy Beukema, Michael Sorna, Karl Selander, et al.,
“A 6.4-Gb/s CMOS SerDes core with feed-forward and
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decision-feedback equalization”, IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2633-2645, Dec. 2005.
