Mohammed A.Alam e-mail:aftab.
Michael H.Azarian e-mail:mazarian@calce.umd.edu
Michael Osterman e-mail:osterman@calce.umd.edu
炸红薯条的做法
Michael Pecht e-mail:pecht@calce.umd.edu
Center for Advanced Life Cycle
倡议书的范文Engineering(CALCE),
University of Maryland,
College Park,MD20742Accelerated Temperature
and Voltage Stress Tests
of Embedded Planar Capacitors With Epoxy–BaTiO3Composite Dielectric
Accelerated temperature and voltage stress tests were conducted on embedded planar capacitors w
ith epoxy–BaTiO3composite dielectric.The failure modes were found to be a sudden increa in the leakage current across the capacitor dielectric and a gradual decrea in the capacitance.The failure mechanisms associated with the failure modes were investigated by performing data analysis and failure analysis.The time-to-failure as a result of a sudden increa in the leakage current was modeled using the Prokopowicz equation.The values of constants of the Prokopowicz equation,n and E a,were deter-mined for the epoxy–BaTiO3composite.The degradation in capacitance was modeled by performing regression analysis.The time-to-failure and degradation models can be ud for the qualification tests of embedded planar capacitors,for the development of new composite dielectric materials,and to improve the manufacturing process of the capacitors.[DOI:10.1115/1.4006704]
Keywords:embedded planar capacitors,polymer–ceramic composites,reliability,tem-perature and voltage stress tests
1Introduction
The basic building blocks of an electronic circuit consist of active and passive components on a printed wiring board(PWB). The passive components consist of capacitors,resistors and inductors,
and in a typical electronic product such as cell phone about80%of the board surface is occupied by the passive components[1].The component density due to passive compo-nents is increasing while PWB designers simultaneously strive for reductions in the number of surface mount components and prod-uct miniaturization.It has been found that the u of embedded passives can reduce the number of surface mount components and hence reduce the PWB size[2].The electrical characteriza-tion of the buried passives can be conveniently performed by impedance spectroscopy and equivalent circuit modeling[3]. Further,manufacturing of the passives and their preferred electrical properties for long term stability has already been inves-tigated[4].
Although there are various embedded passive elements on the PWB,this work will focus only on embedded planar capacitor. This device can be of critical importance since only one or two are found on the PWB as oppod to other passives that are scat-tered all over the PWB with redundancy(in ca of a failure).Em-bedded planar capacitors(Fig.1)are thin laminates that rve both as a power-ground plane and as a parallel plate capacitor in a multilayered PWB.The laminates extend throughout the PWB, reducing the need for a discrete surface mount capacitor adjacent to an integrated circuit(decoupling).PWB space taken up by dis-crete surface mount capacitors and their corresponding intercon-nections can be saved and can lead to miniaturization of
electronic circuits.Embedded capacitors have also been found to provide effective decoupling at microwave frequencies in micro-wave monolithic integrated circuit[5].Further,the capacitors have also been found to reduce the high frequency electromag-netic interference as compared to discrete surface mount capaci-tors[6].The key to the reduction in the number of surface mount capacitors is the low value of parasitic inductance associated with embedded capacitors due to elimination of leads and traces and the thinness of the dielectric[7].
The laminate of an embedded planar capacitor consists of a thin dielectric material sandwiched between copper layers.Polymers such as epoxy and polyimide can be ud as the dielectric material in some applications.Recently,the u of photonsitive polymer has also been investigated that leads to photolithographic forma-tion of embedded capacitors[8].However,the problem of using a polymer dielectric is that it has a low value of dielectric constant. Ceramics such as BaTiO3have a high dielectric constant ($15,000)[9]but their processing temperature is high($850 C) [10]and not compatible with the regular PWB manufacturing pro-cess.To overcome the above limitations,a composite of polymer and ceramic is ud.The advantage of using a polymer–ceramic composite is that it combines the low temperature processability of polymers with the high dielectric constant of ceramics[11]. Composites with dielectric constant as high as150have been obrved using this low t
emperature process[12].Other relevant dielectric properties of the composites have also been investi-gated under dc and acfield and have been found to be suitable for capacitor applications[13].
The most widely ud composite material is the epoxy–BaTiO3 composite.The dielectric constant of BaTiO3is size-dependent and exhibits a peak value when the particle size is clo to140nm [14],so nanoparticles of BaTiO3are preferred in the composite. Further,the dielectric constant of BaTiO3also depends on the processing conditions,nature of dopants,and the frequency and temperature of measurements[15].With an increa in the ce-ramic loading,the effective dielectric constant of the composite
Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the J OURNAL OF E LECTRONIC P ACKAGING.Manuscript received October 7,2011;final manuscript received March18,2012;published online June11,2012. Assoc.Editor:Yi-Shao Lai.
increas and various models has been propod to describe this behavior[16–20].It was obrved that an increa in the BaTiO3 loading beyond55–60%by volume decread the capacitance [21].This was attributed to an increa in the number of voids and pores in the composite when the theoretical maximum packing density approached or exceeded.Typically,for reliability reasons the m
aximum BaTiO3loading should be lower than50%by vol-ume,which limits the maximum dielectric constant of this (epoxy–BaTiO3)composite to about30in commercially available dielectrics[22].
Embedded planar capacitors have many advantages,but the reliability of the devices will determine the breadth and success of their practical application.The capacitors are not reworkable, so the entire PWB will have to be changed in ca of a failure. Further,a drift in the electrical parameters(such as capacitance, dissipation factor,and insulation resistance)of an embedded pla-nar capacitor can affect the performance of the circuit where the capacitors are ud.In previous work performed by us on embed-ded capacitors,we investigated the reliability of the devices under humid conditions[23,24].In the current work,the reliabil-ity of an embedded planar capacitor(with epoxy–BaTiO3dielec-tric)was investigated during accelerated temperature and voltage stress tests.The time-to-failure was modeled by conducting experiments at multiple stress levels and failure analysis was per-formed to investigate the failure mechanism.
2Accelerated Temperature and Voltage Stress Tests Accelerated temperature and voltage stress tests are performed to precipitate failures in dielectric as a result of an increa in the leakage current.The increa in the leakage current can be grad-ual or sudden.A gradual increa in the leakage current is known as thermal runaway(TRA)and a sudden increa in the leakage current is k
nown as avalanche breakdown(ABD)[25].Different mechanisms can be responsible for TRA and ABD depending on the dielectric material.
The tests are generally conducted under highly accelerated stress conditions(as high as200 C and400V in multilayer ce-ramic capacitors),so failures obrved during the tests may not be obrved during the actual operating conditions.But the tests can be ud for qualification,for the development of new dielec-tric materials,and to improve the manufacturing process of the capacitor.
2.1Failure Modes and Mechanisms in BaTiO3Dielectric Ud in Multilayer Ceramic Capacitors(MLCCs).Accelerated temperature and voltage stress tests of MLCCs with BaTiO3 dielectric are common and the results have been documented in literature[26,27].In MLCCs,both TRA and ABD are obrved. TRA has been attributed to the migration of oxygen vacancies(in MLCCs with Cu=Ni electrodes)[28].ABD is obrved in MLCCs with any ceramic dielectric material and has been attributed to defects in the dielectric such as porosity and voids that has a higher concentration of electricfield.An empirical model of time-to-failure as a result of an increa in the leakage current (both TRA and ABD)during accelerated temperature and voltage stress test was propod by Prokopowicz and Vaskas[29].The model is given as
t1
t2
¼
V2
V1
n
exp
E a
k
1
T1
À
1
T2
(1)
where t is the time-to-failure in hours,V is the voltage in volts,n is the voltage exponent,E a is the activation energy,k is the Boltz-mann constant,T is the temperature in Kelvin,and the subscripts 1and2refer to the two stress conditions.There are many publica-tions on lifetime modeling using the Prokopowicz model for pure BaTiO3dielectric ud in MLCCs[30–34].
During temperature and voltage stress tests,a gradual decrea in capacitance is also obrved.The decrea in the capacitance has been attributed to aging in BaTiO3[35].Aging can be described by the equation
C¼C oÀk ln t(2)
where C is the capacitance after time t,C o is the initial capaci-tance,k is the dielectric ageing rate,an
d t is the time.Aging is a gradual process in dielectrics made of BaTiO3and begins after the capacitor’s last excursion beyond the Curie temperature($130 C in BaTiO3).Capacitors can be restored to their original capaci-tance by heating them above their Curie point for a period of time [36].Aging is thermally activated and k increas with an increa in temperature[37].
2.2Possible Failure Modes and Mechanisms in Epoxy–BaTiO3Composite Dielectric Ud in Embedded Planar Capacitors.The results of accelerated temperature and voltage stress tests of embedded planar capacitors(with polymer–ceramic composite dielectric)are not reported in current literature.Hence, the failure modes,failure mechanisms,and failure models are not known for a composite dielectric.In this ction,possible failure modes and mechanisms that can take place in an epoxy–BaTiO3 composite dielectric are discusd.
Thermal runaway is not expected in a composite of epoxy and BaTiO3since oxygen vacancies are not prent in sufficient con-centration in this material[38].However,ABD is expected due to nonuniform electricfield distribution in the composite material. When a composite dielectric is made by mixing a material of high dielectric constant(BaTiO3)with a material of low dielectric con-stant(epoxy),the electricfield is not uniform throughout the ma-terial[39].The electricfield is higher in the epoxy resin than in BaTiO3.This electricfield can be further disrupted by defects such as porosity,
voids,and formation of BaTiO3agglomerates (due to attractive van der Walls forces)[40].Dispersing the BaTiO3nanoparticles uniformly in the epoxy matrix is a critical step in the manufacturing of the capacitors[41].
A standard industrially acceptable test to precipitate defect-related failures in embedded planar capacitors is the hi-pot test [42].In hi-pot test,a potential of up to500V is applied across the embedded planar capacitor for a period of time and the leakage current is monitored.But there are some limitations of this test. This test is just a go=no-go test and hence the result is not a com-prehensive reliability evaluation of the dielectric material.Further hi-pot test does not precipitate wearout failures.Hence,a time-to-failure model as a function of temperature and voltage stress needs to be developed using the Prokopowicz model for this com-posite material.
The capacitance is expected to decrea due to aging in BaTiO3 and an increa in spacing between the plates resulting from thermal deformations in the capacitor laminate[43].The deformations are driven by the thermomechanical stress developed at the interface between the dielectric and the copper foil.Possible sources of the stress can be variations in the ambient temperature,
lf-heating Fig.1Planar capacitor laminate embedded in a PWB
due to power dissipation,and manufacturing process such as solder reflow.Another possible mechanism of decrea in capacitance is re-sidual stress relaxation in the polymer matrix if the dielectric is expod to temperatures above the glass transition temperature (T g )[44].The residual s
tress in the polymer matrix generated during the curing process can be relaxed at temperatures above T g ,leading to an increa in free volume (or free air space)in the polymer.An increa in free volume leads to a decrea in the dielectric constant since the dielectric constant of free space is equal to 1.0.
In this work,temperature and voltage stress tests were con-ducted at multiple stress levels and the values of constants of Pro-kopowicz model are reported for an epoxy–BaTiO 3composite
dielectric.Capacitance data from the same tests were analyzed and a model for the decrea in capacitance was also developed.
3Test Vehicle and Experimental Setup
The test vehicle was a 4-layer PWB (shown in Fig.2)in which layers 1and 4were the signal layers,and the planar capacitor lam-inate formed layer 2(power plane)and layer 3(ground plane).This test vehicle design was first ud in the NCMS embedded ca-pacitor project [45].The power plane was etched at various loca-tions to form discrete capacitors.The test vehicle consisted of two sizes of capacitors,which are termed as group A (small)and group B (large).There were 80capacitors of group A and six capacitors of group B.The capacitances of group A and group B capacitors were abo
ut 400pF and 5nF,respectively.
Each capacitor had the power plane connected to a plated through hole as shown in Fig.3.The ground plane was common for all capacitors and continuous as far as possible (except for the antipads).The dielectric was a composite of epoxy and BaTiO 3.The mean diameter of BaTiO 3particles was about 250nm,and BaTiO 3particles were loaded 45%by volume in the epoxy ma-trix.The dielectric thickness was 8l m and the dielectric constant of this composite was 16at 1kHz.
An experimental tup was designed for biasing the capacitors at an elevated temperature and measuring their electrical parame-ters [46].Thirty-three out of 80capacitors of group A and four out of six capacitors of group B were randomly lected from the test vehicle.Three electrical parameters,capacitance,dissipation fac-tor,and insulation resistance,were measured in situ every hour for the 37capacitors.The capacitance and dissipation factor were measured using an Agilent 4263B LCR meter at 100kHz.Insulation resistance was measured using an Agilent 4339B high resistance meter by applying a bias of 10V and a charge time of 10s.The switching of individual capacitor channels for measure-ments was performed by an Agilent 34980A switching =measuring unit.A ries resistor of resistance 1.1M X was connected in ries to each capacitor to limit the current in the dielectric.
无线鼠标电池
The failure criteria lected were a 20%decrea in capaci-tance,an increa in dissipation factor by a factor of 2,or a drop in insulation resistance to 1.1M X .The insulation resistance fail-ure criterion of 1.1M X was the resistance of the ries resistor connected to each capacitor.Becau of this ries resistor the combined insulation resistance of the capacitor channel was equal to the resistance of the ries resistor even after insulation resist-ance failures.
4Stress Levels for Accelerated Temperature and Voltage Stress Tests
Accelerated temperature and voltage stress tests were con-ducted at multiple stress levels.The temperature at any
stress
Fig.2Test vehicle with group A and group B
capacitors
Fig.3Cross-ctional view of an embedded planar capacitor
condition was less than 125 C since the maximum operating tem-perature of the test board was 130 C.The applied voltage was lected such that the voltage was well below the breakdown volt-age (V BD )of the capacitor dielectric at that temperature.The breakdown voltage of 10embedded capacitors (of group A)was measured at 85 C and 125 C.The results of the breakdown volt-age are shown in Fig.4.It was obrved that the value of V BD decread with an increa in temperature.A reduction in break-down voltage with an increa in temperature can be explained by the free volume theory of the polymer matrix [47].With an increa in temperature,free volume or open air spaces in the polymer increa.Charged particles now get accelerated for a lon-ger distance and have higher energy and hence the breakdown voltage decreas.From the obrved trend and this theory,it implies that breakdown was taking place in the polymer matrix as expected.
缓字组词Failure terminated accelerated temperature and voltage stress tests were conducted at 125 C and 285V,125 C and 250V,and 105 C and 285V that lasted for 500,875,and 2400h,respec-tively.Before the start of the tests,the test vehicle was precon-ditioned at 105 C for 48h to remove any moisture.
梦见毛毛虫5Obrvations
At all stress levels,the failure modes obrved were a sudden decrea in insulation resistance,sudd
en increa in dissipation factor,and a gradual decrea in capacitance.The sudden decrea in insulation resistance and sudden increa in dissipa-tion factor were the result of the same physical ,ABD of the dielectric.A typical plot of insulation resistance is shown in Fig.5.This failure mode is not expected during the nor-mal operating condition due to highly accelerated conditions;however,the results can be ud for qualification tests,develop-ment of new composite materials,and development of new manu-facturing process.
It was obrved that the capacitance degraded logarithmically according to well known aging equation (Eq.(2)).A typical plot of capacitance during aging is shown in Fig.6.
6Modeling the Time-to-Failure
The time-to-failure as a result of the avalanche breakdown was modeled using the Prokopowicz model.The degradation in capac-itance was modeled by performing regression of the capacitance data and computing the dielectric aging rate.
角的度量ppt
6.1Avalanche Breakdown Failures.The time-to-failure of each capacitor was recorded and statistical analysis was per-formed using the Weibull software.At all stress levels,the time-to-failure followed a bimodal distribution,so a mixed Weibull distribution with two subpopulations was ud.A typical prob
ability density function (pdf)plot of time-to-failure is shown in Fig.
7.The two lobes of the pdf plot are referred to as type I and type II here after.No statistical analysis was performed on the time-to-failure data of large capacitors (group B)due to a small sample size.
A plot of unreliability versus time-to-failure at all stress levels is shown in Fig.8.Since failures followed two different distribu-tions,a mixed Weibull with two subpopulations was ud at all stress levels.
The results of the statistical analysis are shown in Table 1for small capacitors (group A).Where b is the shape parameter,g is the scale parameter,and MTTF is the mean-time-to-failure of the Weibull distribution.Bad on the values of b ,it ems that type I and type II failures had a different failure mechanism.The value of b for type I failure is clo to 1implying random
failures
Fig.4Breakdown voltage at 85 C and 125
C
Fig.5Behavior of insulation resistance during aging (of a small capacitor at 125 C and 285
V)
Fig.6Behavior of capacitance during aging (of a large capaci-tor at 125 C and 285
V)
Fig.7Probability density function of time-to-failure of small capacitors (group A)at 125 C,285V
typically caud by overstress conditions.But there were no over-stress conditions since the stress levels were constant throughout the duration of the test.Another possibility is that the failures may be due to defects in the dielectric such as porosity,voids,and agglomer-ation of the ceramic particles.The value of b for type II failure is greater than 1,implying that the failures were the result of a wear-out process so only type II failures were modeled using the Prokopo-wicz model.Using Eq.(1)and MTTF values from Table 1,the value of constants of the Prokopowicz equation was computed.The values of voltage exponent (n )and the activation energy (E a )were found to be 3.89and 1.23eV,respectively,for type I failures.
Although the lifetime was modeled using the data of group A capacitors,this model is applicable to capacitor of any dimensions (area and dielectric thickness)as long as the dielectric material is same.This is becau Prokopowicz model relates the ratio of time-to-failure at two different stress levels (1and 2)for two capacitors with same dimensions
t 1t 2 Same Dimensions ¼V 2V 1
3:89exp 1:23eV k 1T 1À
1
T 2 (3)
However,it has to be noted that for using this model for capaci-tors of other dimensions (other than 8l m dielectric thickness and different than the area of group A capacitor),the time-to-failure of the new capacitor at one stress level (either t 1or t 2)has to be known.
All large capacitors (group B)were found to fail as a result of a sharp drop in insulation resistance within 10h (well below the time-to-failure of small capacitors)at all stress levels.The electric field experienced by the dielectric of both groups (A and B)was the same,so a smaller time-to-failure of large capacitors can be explained by an increa in the number of defects in the dielectric.With an increa in the area of the capacitor,the number of defects in the dielectric should increa,which might have led to a shorter time-to-failure for large capacitors.This implies that the time-to-failure as a result of avalanche breakdown also depends
on area of the capacitor.Another parameter on which the time-to-failure is expected to depend is the dielectric thickness.
A possible future work in this field can be to generalize the Pro-kopowicz model and include the effect of area (a )and dielectric thickness (d ).This generic model is expected to be of the form
t ¼C f ða Þf ðd Þ1V n exp E a
kT (4)where C is a constant and f (a )and f (d )are functions that define
the effect of area and dielectric thickness on time-to-failure,respectively.Another approach can be to find the functional de-pendence of electric field on the time-to-failure,f (E )
t ¼C f ða Þf ðE Þexp
E a
kT (5)This generic model ((4)or (5))can be applied to the capacitor of any dimensions without knowing the time-to-failure of the new capacitor at one stress level (which is the ca with the Prokopo-wicz model).
6.2Capacitance Failures.Regression was performed to compute the values of dielectric aging rate (k )at all stress levels.The results of the regression analysis are shown in Table 2.In some capacitors,th
e value of capacitance started to fluctuate after avalanche breakdown failures.Data of such capacitors were elimi-nated since the objective here was to model the decrea in capac-itance independently of the decrea in insulation resistance.
Failures as a result of a decrea in capacitance (>20%)were obrved in small capacitors (group A)at all stress levels.Histo-grams of decrea in capacitance for small capacitors (group A)for the three test conditions are shown in Fig.9.
No failures as a result of a gradual decrea in capacitance were obrved in large capacitors (group B).The maximum decrea in capacitance of large capacitors was only about 5%.This can be explained as follows:The TTF as a result of a 20%decrea in ca-pacitance can be expresd
as
Fig.8Unreliability versus time-to-failure for small capacitors (group A)
Table 1Statistical analysis of time-to-failure as a result of a sharp drop in IR for small capacitors (group A)Stress levels b g MTTF (h)125 C,285V Type I 1.0130130Type II 6.0444413125 C,250V Type I 1.4188171Type II 5.5739680105 C,285V
Type I 1.6267238Type II
4.9
2937
2702
幽默口才
Table 2Constants of the capacitance degradation curve
Dielectric aging rate (k )
Stress levels Small capacitors Large capacitors 125 C,285V 7.20Â10À11 4.13Â10À11125 C,250V 4.40Â10À1115.1Â10À11105 C,285V
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14.0Â10À11
3.36Â10À
11
Fig.9Decrea in capacitance for small capacitors (group A)
TTF ¼ln
À1
0:2C o k o
(6)
The value of dielectric aging rate (k )was found to be comparable for small and large capacitors (which are shown in Table 2).But the initial value of capacitance (C o )of large capacitors ($5nF)was around 1order of magnitude higher than the initial value of capacitance of small capacitors ($400pF)and hence no failures were obrved in large capacitors during the duration of the test.
7Investigation of the Degradation/Failure Mechanisms
The mechanisms of decrea in capacitance and avalanche breakdown are investigated in this ction.
7.1Decrea in Capacitance.The mechanism of decrea in capacitance can be either an increa in the plate spacing due to thermal stress or a decrea in the dielectric constant due to aging in BaTiO 3.An increa in plate spacing due to thermal deformations is not dominant in this ca since the percentage decrea in capacitance of small and large capacitors was quite different.Further,the degradation in capacitance followed the aging equation,so aging in BaTiO 3is expected to be the degrada-tion mechanism.
The degradation in capacitance was investigated for de-aging (by heating the test vehicle at a temperature clo to the Curie temperature of BaTiO 3).To investigate this,the test vehicle that was aged at 105 C and 285V for 2400h was lected.The aged test board was heated for 20h at a temperature of 130 C (which is clo to the Curie temperature of BaTiO 3)and in situ measure-ments of capacitance were performed.It was obrved that the ca-pacitance continued to decrea as shown in Fig.10.It implies that were no de-aging effects in this composite material as are found in pure BaTiO 3dielectric.It might also be possible that the Curie temperature of BaTiO 3in this composite material was higher than 130 C.But the temperature was not incread beyond 130 C since this was the maximum operating temperature of the PWB.
7.2Avalanche Breakdown.Avalanche breakdown leads to the formation of a conduction path through
the dielectric material.But even after ABD,the final insulation resistance of the dielectric was quite high (of the order of 104–105X ),implying that the dimensions of the failure site were microscopic.The challenge in performing failure analysis was to locate the failure site,which was at an unknown location in the capacitor dielectric.U of nondestructive techniques such as thermal imaging and SQUID (Superconducting Quantum Interference Device)microscopy can possibly locate the failure site,which can be analyzed later
after
Fig.10Behavior of aged capacitor (105 C and 285V for 2400h)of group A during heating at a temperature clo to the Curie tem-perature of BaTiO 3(130
C)
Fig.11Sample preparation steps
