察观
doi: 10.1149/1.3694321
2012, Volume 44, Issue 1, Pages 225-232.ECS Trans. Qiang Shu, Shijian Zhang, JingAn Hao, Yishih Lin, Qiang Wu and Yiming Gu Gate Process Critical Dimension Uniformity (CDU) Control in Sub-45nm Strategy of DoMapper (DoMa) Application and Monitor for rvice Email alerting
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Strategy of DoMapper (DoMa) Application and Monitor for Critical Dimension Uniformity
(CDU) Control in sub-45nm Gate Process
Qiang Shu, Shijian Zhang, Jing’an Hao, Yishih Lin, Qiang Wu, Yiming Gu
Technology R&D, Semiconductor Manufacturing International Corp.
锤子系统
Pudong New Area, Shanghai, P. R. China 201203
As the industry enters 45/40 nm technology node and beyond, the
effective control of polysilicon gate’s critical dimension uniformity
(CDU) becomes more important to device performance. However, to
achieve good uniformity is very challenging since the CDU has shown
high nsitivities to the variations from resist track recipe, scanner
variation, and etcher. It is well known, the DoMapper (DoMa) is a
highly effective tool for the improvement of CDU. In this paper, we
will focus on the t up of a DoMa application and monitor system for
40 nm poly gate CDU improvement. Through the u of a state of the
art immersion exposure tool (ASML 1900Gi), a DoMa application can
successfully improve a gate across wafer CDU by 49% in 40 nm node.
In addition, DoMa is more effective when it is applied at post-etch stage
than at post-litho stage becau it can cover the systematic etch CD
variation. However, when a DoMa recipe is applied at post-etch stage,
曾子是谁at post-litho, the CDU is no longer meaningful. Before the wafer is
etched, we need a new metric to monitor the DoMa performance. A
new DoMa monitoring system by RSQ function at post-litho has been
introduced and the result will be prented in this paper, which can
monitor CD map change by SPC (Statistics Process Control) alarm
function.
画画基础
Introduction
Ultimately tolerances of device electrical performance drive gate linewidth CD uniformity control. It is well known that the gate CDU includes following variations, across chip line variation (ACLV), across wafer CD variation (AWLV), wafer to wafer (WTW) variation, and lot to lot (LTL) variation [1][2]. Especially, the control of ACLV and AWLV is very important, becau the electrical performance degrades and the device no longer functions as intended if the CD varies too much ACLV and AWLV. However, the control of ACLV and AWLV is a very challenging task becau too many sources contribute to ACLV and AWLV, such as, substrate topography, track process variation, aberration in scanner optics, mask and etcher process variation [3].
Since 2009, we have been prenting some papers regarding CMOS logic gate patterning to reduce CD distribution using DoMapper (DoMa) [4]. In that paper, we discusd 65 nm logic gate ACLV and AWLV improvement by DoMa implementation at post-Etch stage, and mentioned the situation when a DoMa recipe is applied at post-etch stage, it is often necessary to skew the CD distribution at post-litho to compensate the post-etch CD variations which are induced from etching and film deposition process. This is due to the fact that the etching bias between post-litho and post-etching CDs across wafer are
metric. Before the wafer is etched, we need a new metric to monitor the DoMa performance. In this paper, our discussion will still focus on ACLV and AWLV corrections using DoMa for 40 nm CMOS logic gate layer. The DoMa monitor system by RSQ function at post-litho and post-etch also has been tup. The new monitor system how to work and how to control the inline RSQ monitor result will also be introduced in the paper.
Experiment and Result with DoMa Application
40 nm Gate CDU Improvement Experiment with DoMa
In all following experiments, the test wafers were generated by a typical 40 nm process flow of logic device. The film stacks of Front-end-of-the-line (FEOL) substrate consist of substrate, gate oxide, poly-Si, silicon nitride, DARC (Dielectric Anti-Reflect Coating) etc. In addition, the litho chemical film stacks usually include organic BARC (Bottom Anti-Reflective Coating) and photoresist. The top-coating is required due to immersion litho in our tests. The wafer substrate together with BARC and resist were optically optimized in order to minimize the reflectivity and suppress the CD swing amplitude. A state-of-the-art ASML TWINSCAN TM immersion ArF scanner was ud for patterning wafers. After etching poly, the photoresist and BARC were stripped. Unless we give a special explan
ation, all ADI (After Develop Inspection) and AEI (After Etch Inspection) CD data in following discussion is Optical CD (OCD) obtained with scatterometry measurements. Before using the scatterometry measurements, the metrology tool went through all necessary qualifications which include CD correlation with CDSEM, CD nsitivity to exposure do and focus, CD linearity and Gauge R&R (Repeatability & Reproducibility) and etc.
A typical 40 nm logic process wafer map with 68 exposure fields is displayed in Figure 1. In order to catch the accurate CD variation information which will be ud in DoMa generation, each field needs to include 9-25 OCD patterns which should be distributed in the field as evenly as possible. Our experiments ud 15 OCD patterns in each field. Since we are interested in generating an effective DoMa rather than minimizing the CD measurements, all OCD patterns (15 x 68 =1,020 readings) were measured in DoMa generation.
Figure 1. A typical wafer map with OCD patterns evenly distributed in a field
Before DoMa application, you have to evaluate the process stability by checking veral important requirements. The requirements are pre-conditions to apply DoMa to your process. Otherwi, the CDU with DoMa might be even wor than the CDU without DoMa if the following important pre-conditions are ignored in DoMa application. The CD differences related to post exposure bake (PEB) temperatures between different units should be ignorable, not only for average temperature but also for the temperature distribution on hot plats.
The CD differences due to different development units should not be detectable.
The tool to tool CD consistency must be well maintained. [Otherwi, different stepper-scanners, different etchers and different OCD tools will introduce more complexity to block the DoMa application.]
The time consistency of CD variation related to stepper-scanner and etcher must be well in control.
In our experiment, ADI CD uniformity by PEB unit is stable, no special CD map, so PEB temperature related variation can be ignored. After confirming the existence of above pre-conditions, the DoMa r
ecipe can be generated by following procedures. First, a focus exposure matrix (FEM) wafer needs to be patterned. By using this FEM wafer, the best focus, best do and the ADI CD nsitivity relative to the exposure do can be obtained. Afterwards, the ADI FEM wafer will be nt to the etcher and the AEI CD nsitivity can be calculated by AEI CD data. The best focus and exposure can be confirmed by this AEI FEM wafer. Second, both ADI and AEI full wafer CDs with best focus and exposure need to be collected. Since an accurate DoMa requires including repeatable systematic CD variations, it is better to u the average CD data from two or more wafers. Finally, the AEI full map CDs and its do nsitivity are nt to CD Analyzer (DoMa software from ASML) and generated a do recipe (DR) including the inter-field and intra-field exposure do adjustments. The DR will be uploaded to the scanner and ready for DoMa recipe application. After that, the AEI CDU with DoMa needs to be collected to confirm DoMa recipe’s effectiveness. Figure 2 shows DoMa recipe creation flow.
Insure tool and process are
孕妇可以吃红枣吗stable enough for DOMA
农村什么赚钱application
DOMA sub-recipe tup
情感空间
Test lot CDU result
confirmation with DOMA
application
Figure 2. DoMa recipe creation flow
40 nm Gate CDU Improvement Experiment Result with DoMa
Bad on the procedures of previous discussion, a DoMa recipe generated by two full wafers AEI CD was successfully applied to the poly wafer process of 40 nm logic devices. The AWLV of AEI CD is mainly induced by the variations of do, focus, flare, numerical aperture, effective source, film sta
ck, PEB temperature, photoresist development and plasma etching. The ACLV of AEI CD mainly consists of the lens optical aberrations, scanning dynamic deviation, flare, mask errors, etc.. However, the AWLV can be effective corrected by means of Do Offt (software, ASML) and the ACLV reduction is realized by slit exposure correction (UniCom, hardware of ASML) and scan exposure correction (DosiCom, software of ASML). The ACLV and AWLV plots of den poly gates with and without DoMa were displayed in Figure 3 and Figure 4, respectively. The experimental data indicates that the improvement of AWLV on our 40 nm poly wafers is very significant, 59% improvement. From Figure 3, it is obvious that the center and edge CD loading (about 3 nm) exists on our wafer. The center and edge CD loading is mainly caud by etch process, which can be corrected by DoMa. The further AWLV reduction is dependent on how to improve the photo tool performance, as focus and do stability, and the etch chamber stability. Nevertheless, the ACLV didn’t display a significant improvement, 27% improvement, as shown in Figure 4. The global CDU (AWLV+ACLV), which is defined as the square root of the quadratic sum of AWLV and ACLV, is improved by 49%, as shown in Figure 5.
开封相国寺
Figure 3. AWLV improvement for den poly gates of 40 nm logic device
W/O DOMA
Figure 4. ACLV improvement for den poly gates of 40 nm logic device
