AEC - Q002 Rev A
学生安全August 25, 2000长城的
GUIDELINES
FOR
STATISTICAL YIELD
ANALYSIS
Component Technical Committee
Automotive Electronics Council
AEC - Q002 Rev A
August 25, 2000 Automotive Electronics Council
世界上下五千年
Component Technical Committee
Acknowledgment
Any document involving a complex technology brings together material and skills from many sources. The Automotive Electronics Council would especially like to recognize the following significant contributors to the development of this revision of this document:
Majdi Mortazavi DaimlerChrysler (256)464-2249
Brian Jendro DaimlerChrysler (256)464-2980
Robert V. Knoell Visteon Corporation (313)248-1116
Gerald E. Servais Delphi Delco Electronics Systems (765)451-7923
Kevin Hankins Delphi Delco Electronics Systems (765)451-7670
Nick Lycoudes Motorola (408)413-3343 raqa01@m
Philippe Briot PSA, Peugeot, Citroën 33 01 41 36 7849 p-briot@calvanet.calvacom.fr
Mark Gabrielle On Semiconductor (602)244-3115 mark.
Component Technical Committee
GUIDELINES FOR STATISTICAL YIELD ANALYSIS Text enhancements and changes made since the last revision of this
document are shown as underlined areas
1.SCOPE
This guideline is intended for u as a method for detecting and removing abnormal lots of material and thus ensuring the quality and reliability of the ICs supplied as meeting AEC - Q100 or 101. The principles described in this guideline are applicable to packaged or unpackaged die.
1.1Purpo
This guideline describes a method, utilizing statistical techniques, of identifying a wafer, wafer lot or asmbly lot that exhibits an unusually low yield or an unusually high bin failure rate. Experience has shown that wafer and asmbly lots exhibiting the abnormal characteristics tend to have
generally poor quality and can result in significant system reliability and quality problems.
Note: For best statistical yield limits (SYL) and statistical bin limits (SBL) results, u test limits
bad on PAT Limits as described in AEC Q001.
1.2 References
AEC - Q001 Guidelines For Part Average Testing
AEC - Q100 Stress Test Qualification For Integrated Circuits
AEC - Q101 Stress Test Qualification For Discrete Semiconductors
2.DEFINITIONS
2.1PAT Limits
Part average test limits established per AEC - Q001.
3.METHOD FOR ESTABLISHING STATISTICAL YIELD LIMITS (SYL) AND STATISTICAL BIN
LIMITS (SBL)
3.1Detailed Description For Basic Wafer / Wafer Lot / Asmbly Lot Level Yield Limits
Collect data from at least six lots and determine the mean and sigma value for the percentage of
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devices passing per lot and the percentage of devices failing each bin-out per lot (lot as ud here could mean each wafer, a wafer lot or an asmbly lot). Early in production of a part, when data
Component Technical Committee
from six lots is not available, data from characterization/matrix lots may be ud. This data shall
be updated as soon as production data is available. This early data shall be reviewed and updated using current data at least every 30 days during the first 6 months of production. The current data ud shall include the data available since the last update or at least the last 8 lots. Older data shall not be ud. After the first 6 months of production the limits shall be updated on a quarterly (every
3 months) basis. With this data determine the SYL and SBL (both on a wafer, wafer lot and
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asmbly lot basis) as follows:
SYL1 = Mean - 3 Sigma
SBL1 = Mean + 3 Sigma
SYL2 =Mean - 4 Sigma
SBL2 = Mean + 4 Sigma
Any wafer or lots that fall below SYL1 or exceed SBL1 shall be held for engineering review. In
addition, lots that fall below SYL2 or exceed SBL2 may be impounded and require customer
notification before relea, if specified in the applicable procurement document. Analysis shall be performed on failures to determine the failure mechanism(s) causing the abnormal failure rates.
3.2Records
The supplier shall maintain records on all wafers, wafer lots and asmbly lots that fall below SYL1 or exceed SBL1. This data shall include the root cau for the yield problem and corrective action taken to prevent reoccurrence of the problem. It should also include any special testing or screens that were performed on the wafer, wafer lot or asmbly lot and the customer that approved the
shipment of the parts in question.
4. CUSTOMER NOTIFICATION
4.1Procedure For Customer Notification
Before the customer is notified, the supplier shall have determined the failure mechanism(s) and,
bad on his experience, determine the corrective action required to prevent a reoccurrence of the condition in future product. The supplier shall also prent data on a reasonable expectation of the riousness of the failure mechanism(s) and it’s impact on quality and reliability. Included in this data should be a plan for additional tests and screens which could provide the ur with reasonable certainty that the product he receives will be at least equal to normal product.
4.2Customer Respon
The customer rerves the right to reject material that falls below SYL2 or exceeds SBL2 if the
supplier data does not satisfy his concerns about the quality and reliability of the product.
4.3 If Customer Is Not Known
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If the supplier does not know who the customer is and customer approval can not be obtained, the parts from the lots in question (lots falling below SYL2 or exceeding SBL2) shall not be supplied to distributors as meeting AEC - Q100 or Q101.
Component Technical Committee
Revision History
Rev #Date of change Brief summary listing affected paragraph
小儿惊厥-July 31, 1997Initial relea
A Aug. 25, 2000Added Paragraph 1.2, Paragraph 1, 2.1, and 4.3 revid.
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