Agilent HDMP-1687
Four Channel SerDes Circuit for Gigabit Ethernet and Fibre Channel
Data Sheet
Functional Description
The HDMP-1687 is a four channel SERDES device. HDMP-1687 is in a 208-ball TBGA package with four 1.0625/1.25 Gbps rial I/O. This integrated circuit provides a low-cost, low-power, small-form-factor physical-layer solution for multi-link Gigabit Ethernet/Fibre Channel interfaces. This IC may be ud to directly drive copper cables, or it may be ud to interface with opti-cal transceivers. Each IC contains transmit and receive channel cir-cuitry for all four channels.
The transmitter ction accepts
10-bit-wide parallel TTL data on each channel and rializes it into
a high-speed rial stream. The parallel data is expected to be
8B/10B encoded (or equivalent). Four banks of parallel data are latched into the input registers of the transmitter ctions on the ris-ing edge of RFCT.
Receive data are latched out with parate clock pins for each chan-nel. The pins may be single 106.25/125 MHz TTL clock outputs RC [0:3] [1] or dual 53.125/62.5 MHz TTL pairs RC [0:3] [0:1] to rve legacy applications where single SerDes devices were ud
before. The receive clock mode
lect (RCM0) pin is ud to de-
fine the designer’s choice.
RCM0 Receive Clock Mode
0half speed dual clocks
1full speed single clocks
The SYNC pin enables bytesync
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detection on all four channels.
When a comma character is
detected on any channel, its corre-
sponding SYN [0:3] pin goes high.
A single LOOP pin is provided for
all channels to enable the local
loopback function.
HDMP-1687 Block Diagram
The following is a description of
the blocks in each channel. Ex-
cept for the transmit PLL ction,
circuits for the channels are inde-
pendent. Figure 1 shows how this
IC may be connected to a protocol
device that controls four channels.
Each channel of the four channel
SERDES (Figure 2) was designed
to transmit and receive 10-bit-
wide characters over dedicated
differential high-speed lines. The
parallel data applied to the trans-
mitter is expected to be encoded爱拼才会赢作文
per the 8B/10B encoding scheme,
with special rerve characters for
link management purpos. Other
encoding schemes will also work
as long as they provide dc balance
and sufficient transition density.
In order to accomplish this task,
the SERDES circuitry incorporates
the following:
Features
•Four ANSI x3.230- 1994 Fibre Chan-
nel (FC-O) or IEEE 802.3z Gigabit
Ethernet compatible SerDes in
a single package
•Supports rial data rates of 1062.5
MBd (Fibre Channel) & 1250 MBd
(Gigabit Ethernet)
•Bad on X3T11 Fibre Channel
”10 bit specification“
•Us reference clock (RFCT) for Tx
data latching
•Half or full speed Rx clocks
•5-Volt tolerant TTL I/Os
•Low power consumption
•208 ball, 23 mm TBGA package
•Single +3.3 V power supply我们这个家
•1.5 kV ESD protection on all pins
•Equalizers on inputs
•Copper drive capability
•Buffered line logic outputs
Applications
•1250 MBd Gigabit Ethernet high
density ports
•1062.5 MBd Fibre Channel interface
•Mass storage system I/O channel
•Work station/rver I/O channel
•FC interface for disk drives and
arrays
•Serial backplanes
•
Clusters
•TTL parallel I/Os
•High-speed pha locked loops •Parallel-to-rial converter •High-speed rial clock and data recovery circuitry •Comma character recognition circuitry for 8B/10B •Character alignment circuitry •Serial-to-parallel converter
PARALLEL INPUT LATCH
The transmitter accepts 10-bit wide single-ended TTL parallel data at inputs TX [0:3] [0:9]. The RFCT pin is ud as transmit byte clock. The TX [0:3] [0:9] and RFCT signals must be properly aligned, as shown in Figure 3. RFCT is also ud as a clean fre-quency reference for the receiver PLLs.
TX PLL/CLOCK GENERATOR
The transmitter Pha Locked Loop and Clock Generator (TX PLL/CLOCK GENERATOR) block generates all internal clocks needed by the transmitter ction to perform its functions. The clocks are bad on the supplied reference clock (RFCT). RFCT is ud as the frequency reference clock for the PLL as well as for the incoming data latches. The RFCT clock is multiplied by 10 to generate the rial rate clock necessary for clocking the high speed rial outputs.
FRAME MUX
The FRAME MUX accepts the
10-bit wide parallel data from the INPUT LATCH. Using internally generated high speed clocks, this parallel data is multiplexed into rial data streams. The data bits are transmitted quentially, from TX [0:3] [0] to TX [0:3] [9]. SERIAL OUTPUT SELECT
The OUTPUT SELECT block provides for an optional internal loopback of the high speed rial signal for testing purpos.In normal operation, LOOP is t
low and the rial data stream is
placed at SO [0:3]±. When
wrap-mode is activated by tting
LOOP high, the SO [0:3]± pins
are held static at logic 1 and the
rial output signal is internally
wrapped to the INPUT SELECT
block of the receiver ction.
SERIAL INPUT SELECT
The INPUT SELECT block deter-
mines whether the signal at
SI [0:3]± or the internal loop-
back rial signal is ud. In
normal operation, LOOP is t
low and the rial data is ac-
cepted at SI [0:3]±. When LOOP
is t high, the outgoing high
speed rial signal is internally
looped-back from the transmitter
ction to the receiver ction.
This feature allows parallel
loopback testing, exclusive of the
transmission medium.
RX PLL/CLOCK RECOVERY
The RX PLL/CLOCK RECOVERY
block is responsible for frequency
and pha locking onto the in-
coming rial data stream and
recovering the bit and byte
clocks. The Rx PLL continually
frequency locks onto the refer-
ence clock, and then pha locks
onto the lected input data
stream. The frequency lock part
of the PLL is shared among all
channels. Pha locking is per-
formed parately on each chan-
nel. An internal signal detection
circuit monitors the prence of
the input, and invokes the pha
detection once the minimum
differential input signal level is
乔布斯和比尔盖茨supplied (AC Electrical Specifica-
tions). Once bit locked, the re-
ceiver generates the high speed
sampling clock at rial data
rates for the input sampler.
SERIAL INPUT SAMPLER
The INPUT SAMPLER converts
the rial input signal into a high
speed rial bit stream. In order
to accomplish this, it us the
high speed rial clock recovered
from the RX PLL/CLOCK RECOV-
ERY block. This rial bit stream
is nt to the FRAME DEMUX
AND BYTE SYNC block.
FRAME DEMUX, BYTE SYNC
The FRAME DEMUX, BYTE
SYNC block is responsible for
restoring the 10-bit parallel data
from the high speed rial bit
stream. This block is also re-
静待黎明sponsible for recognizing the
comma character (K28.5+) of
positive disparity (0011111xxx).
When recognized, the FRAME
DEMUX, CHAR SYNC block
works with the RX PLL/CLOCK
RECOVERY block to properly
lect the parallel data edge out
of the bit stream so that the
comma character starts at bit
RX [0:3] [0]. When a comma
character is detected and realign-
ment of the receiver byte clock
RC [0:3] [0:1] is necessary, this
clock is stretched, not slivered, to
the next possible correct align-
ment position. This clock will be
fully aligned by the start of the
cond 4-byte ordered t. The
cond comma character received
will be aligned with the rising
edge of RC [0:3] [1] and will
follow it with a delay. This delay
guarantees hold time at the re-
ceiving ICs input latches. Comma
characters of positive disparity
入盆时间
must not be transmitted in con-
cutive bytes to allow the re-
ceiver byte clocks to maintain
their proper recovered frequen-
cies.
PARALLEL OUTPUT DRIVERS
The OUTPUT DRIVERS prent
the 10-bit parallel recovered data
byte properly aligned to the
receive byte clocks RC [0:3]
[0:1] as shown in Figure 5.
The output data buffers provide
single ended TTL compatible
signals.
Figure 1. Typical application using HDMP-1687.
Figure 2. Block diagram of HDMP-1687.
SO [0:3]±
CAP0LOOP
RFCT
RC[0:3][1]
RX [0:3][0:9]
TX[0:3][0:9]
CAP1
SYNC
SYN [0:3] SI [0:3]±
CC Symbol Parameter Units Min.Typ.
Max.
T txtup Tx Input Setup Time ns 1.5T txhold Tx Input Hold Time ns 0.5
t_txlat [1]
Transmitter Latency
ns 2.3bits
2.8Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of the transmit byte clock, RFCT) and the transmission of the first rial bit of that parallel word (defined by the edge of the first bit transmitted).
Figure 3. Transmitter ction timing.
Figure 4. Transmitter latency.
TX [0:3] [0:9]
RFCT 1.4 V
2.0 V
0.8 V
Timing Characteristics for Fibre Channel – Transmitter Section T = 0°C Ambient to +85°C Ca, V CC = 3.15 V to 3.45 V Symbol Parameter Units Min.Typ.
Max.
T txtup Tx Input Setup Time ns 2.0T txhold Tx Input Hold Time ns 1.5
t_txlat [1]
Transmitter Latency
ns 3.8bits
4.0Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of the transmit byte clock, RFCT) and the transmission of the first rial bit of that parallel word (defined by the edge of the first bit transmitted).
CC Symbol Parameter Units Min.
Typ.
Max.f_lock Frequency Lock at Powerup µs 500b_sync [1,2]Bit Sync Time bits 2500
t rxtup RX [0:3][0:9] Output Setup Time (Data Valid Before Clock)ns 2.5t rxhold RX [0:3][0:9] Output Hold Time (Data Valid After Clock)ns 2.0T duty RC [0:3][0] and RC [0:3][1] Duty Cycle %4060t A-B Rising Edge Time Difference between RBC0 and RBC1 (Half Rate)ns 7.58.5
t_rxlat [3]Receiver Latency
ns 20.7bits
26.0
心肌炎的治疗Notes:
1.This is the recovery time for input pha jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2.Tested using C PLL = 0.1 µF.
3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first rial bit of a parallel data word (defined as the edge of the first rial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC[0:1]).
RX [0:3] [0:9]
RC [0:3] [1]SYNC
RC [0:3] [0]
Timing Characteristics for Fibre Channel – Receiver Section T = 0°C Ambient to +85°C Ca, V CC = 3.15 V to 3.45 V Symbol Parameter Units Min.
Typ.
Max.f_lock Frequency Lock at Powerup µs 500b_sync [1,2]Bit Sync Time bits 2500
t rxtup RX [0:3][0:9] Output Setup Time (Data Valid Before Clock)ns 3.0t rxhold RX [0:3][0:9] Output Hold Time (Data Valid After Clock)ns 1.5T duty RC [0:3][0] and RC [0:3][1] Duty Cycle %4060t A-B Rising Edge Time Difference between RBC0 and RBC1 (Half Rate)ns 8.99.9
中国历史手抄报t_rxlat [3]Receiver Latency
ns 22.4bits
28.0
Notes:
1.This is the recovery time for input pha jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2.Tested using C PLL = 0.1 µF.
3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first rial bit of a parallel data word (defined as the edge of the first rial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC[0:1]).
Absolute Maximum Ratings
T A = 25°C, except as specified. Operation in excess of any one of the conditions may result in permanent damage to this device. Continuous operation at the minimum or maximum ratings is not recommended.Symbol Parameter Units Min.Max.V CC Supply Voltage V –0.5 4.0V IN,TTL TTL Input Voltage
V –0.7
V CC + 2.8V IN,HS_IN HS_IN Input Voltage (Differential)V 2.2I O,TTL TTL Output Sink / Source Current mA ± 13T stg Storage Temperature °C –65+150T j Junction Temperature °C 0+125T C
Ca Temperature
°C
0+95
Guaranteed Operating Rates
T = 0°C Ambient to +85°C Ca, V CC = 3.15 V to 3.45 V Parallel Clock Rate (MHz)Serial Baud Rate (MBaud)
Min.Max.Min.Max.124.0126.012401260Gigabit Ethernet 105.25107.25
1052.5
1072.5
Fibre Channel
Figure 6. Receiver latency.
RX [0:3] [0:9]SI [0:3] ±RC [0:3] [1]
Figure 5b. Receiver ction timing (single receive clock).
RX [0:3] [0:9]
RC [0:3] [1]
