One major challenge in optimization of dc/dc power conversion solutions today is feedback loop compensation. To the laymen of dc/dc power conversion circuits, this concern can be not only difficult to understand, but a highly intimidating matter to deal with. Various effects of feedback loop stability occur with application of feedback compensation, which, if not properly calculated, can cau instability and regulation failure to occur. This application note helps to clarify the more advanced Type-III feedback loop compensation considerations in voltage-mode buck converter applications, which are viewed as inherently more stable when compared to current-mode conversion topologies.
Most designers believe the application of ceramic output capacitors is a good design decision, for both their low cost, abundance of suppliers, and the inherently low ESR. Ceramic capacitors are indeed a good choice for converter output filtering, where relatively low capacitance is required. Ceramic capacitors offer low Equivalent Series Resistance (ESR) that reduces output ripple. However, the inherently low ESR of the typical ceramic output capacitor necessitates the u of a Type-III compensa
tion network. The Type-III compensation network, which is more complicated than Type-II, will be explained in the following text.
Buck Converter System Block Diagram
The system block diagram of a Buck-Converter is shown in figure 1 where V IN and V OU t are converter input and output voltage respectively. The Error Amplifier and its accompanying passive components compri the compensation network (compensation). The focus of this application note is the proper lection of the passive components in order to meet compensation goals. Output of the compensation network is the analog control signal Vc. The Pul-width-Modulator (Modulator) generates a duty-cycle D that is proportional to Vc. Duty-cycle control D of power switches in conjunction with the filter produce the desired voltage V OUT from V IN .
Figure 1. System Block Diagram of Buck-Converter
Pul-Width Modulator (Modulator) Compensated Error
Amplifier
(Compensation)Power switches &
LC output filter (Power stage) V IN
Feedback
给自己的安慰V REFERENCE带鱼怎么处理干净
V OUT
D Vc
Open-Loop Respon
System respon from the input of the Modulator to the output of the power stage is called “Open-Loop Respon”. It is shown in figure 2. The LC output filter gives ri to a “Double-Pole” that has a -180 degrees pha shift. Double-Pole frequency f LC is given by:
LC
fLC π21= (1)
The ESR of output capacitor C gives ri to a “ZERO” that has a +90 degree pha shift. ESR ZERO
frequency f ESR is given by:
ESR
C fESR ..21π= (2)
Figure 2 shows two plots. The top plot is reprentative of the Open-Loop gain and the lower plot shows the relevant pha. When the output capacitor is a small ceramic type, f ESR can be significantly larger than f LC . In this ca, the pha of the open-loop reaches -180 degrees before the ESR Zero brings the pha to -90 degrees (e figure 2).
Gain (dB)0 (deg)
绮丽的近义词0 (dB)-40dB/dec
Pha (deg)-180 (deg)20log(Vin/Vramp)f
-20dB/dec
-90 (deg)
LC ESR f >>f LC
大雨还在下歌词
+45deg/dec
> -90deg/dec
Figure 2. Gain/Pha of the Open-Loop Respon with ceramic output capacitor
Goals of Compensation
The goal of compensation is to design a feedback system such that the converter will be stable and will quickly regulate the output against changes in input voltage or load conditions. Quick respon requires that the Loop 0dB cross-over frequency “fc” (also known as bandwidth) be as high as practical. In general, compensation is designed such that (fs/10)<fc<(fs/5); where fs is the switching frequency of the converter. Stability criterion requires that the pha margin corresponding to “fc” be greater than 45 degree where
Pha Margin = 180 degree + pha of Loop Gain
In esnce we have to shape the Gain/Pha of the Error Amplifier such that when combined with Gain/Pha of the Open-Loop of figure 2 it satisfies the above requirements.
Type-III Compensation
Type-III compensation is realized by connecting resistors/capacitors to a controller’s integral Error Amplifier as shown in figure 3. A nomenclature consistent with Sipex datasheet is ud. Transfer function of Type-III has two “Zeros” and two “Poles” at the frequencies shown in figure 3. The combined effect of the Zeros results in a 180 degree pha boost. This pha boost is necessary to counter the 180 degree pha lag due to the output filter double-Pole shown in figure 2 and generate the required pha margin. In order to simplify the solution for the frequency of the 2nd Zero and 1st Pole, components must be chon so that CZ2>>CP1 and R1>>RZ3. Further simplification can be made by making the frequency of the two Zeros coincide. As stated above, the goal is to locate the Poles and Zeros of the compensation such that the desired crossover frequency and corresponding pha margin is obtained.
-
+
CZ2RZ2CP1
R1
CZ3RZ3Vreference Vcomp
Vout
1/(6.28 RZ3CZ3)
1/(6.28 RZ2 CZ2) Gain (dB)
frequency (Hz)
20log(RZ2/R1)
frequency (Hz)
Pha (degree)
-90
极的组词+901/(6.28 R1 CZ3) 1/(6.28 RZ2 CP1) 20log(RZ2/RZ3)Conditions: CZ2>>CP1, R1>> RZ3
Maximum boost
possible is 180 degree
Figure 3. Type-III compensation and its associated gain/pha plots.
Six resistors and capacitors, when connected to the Error Amplifier as shown, create a type-III compensation network. Component nomenclature is the same as commonly ud in Sipex datasheets. The frequency of the cond “Zero” and first “Pole” are simplified solutions bad on choosing CZ2>>CP1, R1>>RZ3.
Procedure for Calculating Type-III Components
As was mentioned, when a ceramic output capacitor is applied, the open loop pha usually drops to -180 degrees or clo to it. In order to achieve the required pha margin of 45 degrees or greater (i.e., pha greater than -135 degrees), a type-III compensation is needed to provide sufficient pha boost. Let’s assume that the pha of open-loop system gain is the lowest possible, i.e., 180 degrees. To get the minimum required clod-loop pha-margin of 45 degrees the compensation must provide a +45 degree pha margin (i.e., a boost of 95 degrees). In order to maximize the boost, Poles and Zeros must be placed as far apart as possible. We can now outline a step-by-step procedure for calculating component values, as follows:
1.) Let R1=68.1k Ω. This value generally provides a satisfactory solution and helps meet the requirement R1>>RZ3
2.) Place the cond Zero at 60% of output filter’s double-Pole frequency and solve for CZ3:
LC偏光太阳镜和普通太阳镜的区别
R zsf CZ 1113•
•=……………………………..… (3) Where
L and C are output inductance and capacitance respectively
zsf is Zero scale factor = 0.6
3.) To t fc to the desired value u the following equation and calculate RZ2 from:
Vin Vramp x CZ fc C L fc RZ 32122)(2•••+••••=ππ (4)
Where
V RAMP is the ramp amplitude and V IN is converter’s input voltage
f c is typically t at 1/5 to 1/10 of switchin
g frequency f s 4.) Set the first Zero to coincide wit
h the cond Zero and calculate CZ2 from:
LC
RZ zsf CZ 1212••=……………………………. (5) 5.) Set the first Pole at switching frequency of the converter f s and solve for CP1:
在线excel
fs
隶书创作
RZ CP •••=2211π………………………………… (6) 6.) Set the cond Pole also at f s and solve for RZ3:
fs
CZ RZ •••=3213π (7)
