Features Array•Also known as SMCS332SpW
• 3 identical bidirectional SpaceWire links allowing
–full duplex communication
–transmit rate from 1.25 up to 200 Mbit/s in each direction
•Derived from the TSS901E-SMCS332 triple IEEE 1355 high speed controller –Known anomalies of the TSS901E chip corrected
–Slightly different startup behavior
•COmmunication Memory Interface (COMI)
–autonomous access to a communication memory
•HOst Control Interface (HOCI)
–gives read/write access to the AT7911E configuration registers
–gives read/write access to the SpaceWire channels
•Arbitration unit
–Allows two AT7911E to share one Dual Port RAM without external arbitration •Scalable databus width
–8/16/32 bit width available
–allows flexible integration with any CPU type
•Allows Little endian and Big endian configuration
•Performance
–At 3.3V: 100 Mbit/s full duplex communication in each direction
–At 5V: 200 Mbit/s full duplex communication in each direction
•Operating range
–Voltages
•3V to 3.6V
•4.5V to 5.5V
–Temperature
•- 55°C to +125°C
•Maximum Power consumption
–At 3.6V with a 15MHz clock : 0.4 W
–At 5.5V with a 25 MHz clock : 1.7 W
•Radiation Performance如何面对压力
–Total do tested successfully up to 50 Krad (Si)
–No single event latchup below a LET of 80 MeV/mg/cm2
•ESD better than 2000V
•Quality Grades :
五年级下册语文第二课–QML-Q or V with SMD
•Package : 196 pins MQFPL
•Mass : 12grams
2
7737B–AERO–05/08
AT7911E
1.Description
The AT7911E provides an interface between three SpaceWire links according to the SpaceWire standard ECSS-E-50-12A specification and a data processing node consisting of a Control Pro-cessing Unit and a communication data memory.
The AT7911E was designed by EADS Astrium in Germany under the name 'SMCS332SpW" for "Scalable Multi-channel Communication Subsystem for SpaceWire". It is manufactured using the SEU hardened cell library from Atmel MG2RT CMOS 0.5µm radiation tolerant a of gates technology.
For any technical question relative to the functionality of the AT7911E plea contact Atmel technical support at assp-applab.hotline@ .
This document shall be read in conjunction with EADS Astrium 'SMCS332SpW Ur Manual'. The complete ur manual of the AT7911E also called SMCS332SpW is available at .
The AT7911E provides hardware supported execution of the major parts of the interprocessor communication protocol, particularly:•Transfer of data between two nodes of a multi-processor system with minimal host CPU intervention
•Execution of simple commands to provide basic features for system control functions •
Provision of fault tolerant features.
Target applications are heterogeneous multi-processor systems supported by scalable inter-faces in
cluding the little/big endian byte swapping. The AT7911E connects modules with different processors (e.g. TSC695F, AT697E and others). Any kind of network topology could be realized through the high speed point-to-point SpaceWire links (e the ction ‘Applications’). It can also be ud for modules without any communication features such as special image com-pression chips, some signal processors, application specific programmable logic or mass memory.
The AT7911E may also be ud in single board systems where standardid high speed inter-faces are needed and systems containing "non-intelligent" modules such as A/D-converter or nsor interfaces which can be asmbled with the AT7911E thanks to the "control by link" feature.
3
7737B–AERO–05/08
AT7911E
Figure 1. AT7911E Block Diagram
The AT7911E is supported by VSPWorks from Wind River, a commercially available distributed real-time kernel. It is a multi-tasking as well as a multi-processor Operating System. The main goals are to enable programming at a higher level to configure and to perform communication and to administer the tasks on a board with multiple process running in parallel.
The VSPWorks kernel supports multiple processors and application specific chips, e.g. the TSC21020, the Sparc TSC695F, the Thus it is possible to run a heterogeneous multiprocessor system with a single Operating System without consideration of the hardware platform.
照相机简笔画
4
7737B–AERO–05/08
AT7911E
2.Pin Configuration
Table 1. Pin assignment
Pin Number
Name Pin Number Name Pin Number Name Pin Number Name Pin Number Name
1PLLOUT 41VCC 81HDATA28121CMDATA0161GND 2GND 42GND 82HDATA29122CMDATA1162CMDATA273VCC 43HDATA083VCC 123CMDATA2163CMDATA284CLK 44HDATA184GND 124VCC 164CMDATA295RESET*45HDATA285HDATA30125GND 165CMDATA306CLK1046HDATA386HDA
TA31126CMDATA3166CMDATA317HOSTBIGE 47HDATA487CPUR*127CMDATA4167GND 8TCK 48HDATA588SES0*128CMDATA5168GND 9TMS 49HDATA689SES1*129VCC 169VCC_3VOLT 10TDI 50VCC 90SES2*130GND 170GND 11TRST*51GND 91SES3*131CMDATA6171GND 12TDO 52HDATA792CAM 132CMDATA7172VCC 13VCC 53HDATA893COCI 133CMDATA8173GND 14GND 54HDATA994COCO 134VCC 174GND 15HSEL*55HDATA1095CMCS0*135GND 175NC 16HRD*56HDATA1196CMCS1*136CMDATA9176LDI117HWR*57VCC 97VCC 137CMDATA10177LSI118HACK 58GND 98GND 138CMDATA11178LDO119HINTR*59HDATA1299CMRD*139CMDATA12179LSO120VCC 60HDATA13100CMWR*140CMDATA13180LDI221GND 61HDATA14101CMADR0141CMDATA14181LSI222HADR062HDATA15102CMADR1142VCC 182NC 23HADR163HDATA16103CMADR2143GND 183VCC 24HADR264HDATA17104CMADR3144CMDATA15184VCC 25HADR365VCC 105CMADR4145CMDATA16185VCC 26HADR466GND 106VCC 146CMDATA17186LDO227HADR567HDATA18107GND 147CMDATA18187LSO228HADR668HDATA19108CMADR5148CMDATA19188LDI329HADR769HDATA20109CMADR6149CMDATA20189LSI330VCC 70HDATA21110CMADR7150VCC 190LDO331GND 71HDATA22111CMADR8151GND 191LSO3
32BOOTLINK 72HDATA23112CMADR9152CMDATA21192TIME_CODE_SYNC 33SCMSADR073VCC 113CMADR10153CMDATA22193GND 34SMCSADR174GND 114CMADR11154CMDATA23194GND 35SMCSADR275HDATA24115VCC 155VCC 195VCC 36SMCSADR376HDATA25116GND 156GND 196
GND
37SMCSID077HDATA26117CMADR12157CMDATA2438SMCSID178VCC 118CMADR13158CMDATA2539SMCSID279GND 119CMADR14159CMDATA2640
SMCSID3
80
HDATA27
120
CMADR15
160
VCC
5
7737B–AERO–05/08
AT7911E
3.Pin Description
Table 2. Pin description
Signal Name (1)(3)
Type (2)(4)
Function
5V ± 0.5V
max. output current [mA]
鹦鹉学舌的意思3.3V ± 0.3V max. output current [mA]
load [pF]
HSEL*I Select host interface HRD*I host interface read strobe HWR*I host interface write strobe
HADR(7:0)I AT7911E register address lines. The address lines will be ud to access (address) the AT7911E registers.HDATA(31:0)
IO/Z AT7911E data
3 1.550HACK O/Z host acknowledge. The AT7911E deasrts this output to add waitstates to an AT7911E access. After AT7911E is ready this output will be asrted.3 1.550HINTR*O/Z host interrupt request line
3
1.5
50
SMCSADR(3:0 )I Address. The binary value of the lines will be compared with the value of the ID lines.
SMCSID(3:0)I ID lines: offers possibility to u sixteen AT7911E within one HSEL*
水墨画入门HOSTBIGE手绘墙
I
0: host I/F Little Endian 1: host I/F Big Endian BOOTLINK I
0: control by host 1: control by link
CMCS(1:0)*O/Z
Communication memory lect lines. The pins are
asrted as chip lects for the corresponding banks of the communication memory.孕妇怕冷
6
3
25
CMRD*O/Z Communication memory read strobe. This pin is asrted when the AT7911E reads data from memory.
6325CMWR*O/Z Communication memory write strobe. This pin is asrted when the AT7911E writes to data memory.
6325CMADR(15:0)O/Z Communication memory address. The AT7911E outputs an address on the pins.
6325CMDATA(31:0)
IOZ Communication memory data. The AT7911E inputs and outputs data from and to com. memory on the pins.3
1.5
25
COCI I Communication interface 'occupied' input signal COCO O Communication interface 'occupied' output signal 3
1.5
50
CAM I Communication interface arbitration master input signal 1: master 0: slave
CPUR*O CPU Ret Signal (can be ud as ur defined flag)3 1.550SES(3:0)*O Specific External Signals (can be ud as ur defined flags)3
1.5
50
respond
LDI1I Link Data Input channel 1LSI1I Link Strobe Input channel 1LDO1
O
Link Data Output channel 1
12
6
25
