Features
•Stacked device (two 512Mb die)•SPI-compatible rial bus interface
•Single and double transfer rate (STR/DTR)•Clock frequency
–133 MHz (MAX) for all protocols in STR –90 MHz (MAX) for all protocols in DTR
•Dual/quad I/O commands for incread through-put up to 90 MB/s
•Supported protocols: Extended, Dual and Quad I/O both STR and DTR •Execute-in-place (XIP)
•PROGRAM/ERASE SUSPEND operations
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•Volatile and nonvolatile configuration ttings •Software ret
•Additional ret pin for lected part numbers
•3-byte and 4-byte address modes – enable memory access beyond 128Mb
•Dedicated 64-byte OTP area outside main memory –Readable and ur-lockable •
Era capability –Die Era
董事会职责和权限–Sector era 64KB uniform granularity –Subctor era 4KB, 32KB granularity •Era performance: 400KB/c (64KB ctor)•Era performance: 80KB/c (4KB sub-ctor)•Program performance: 2MB/c •
Security and write protection
–Volatile and nonvolatile locking and software write protection for each 64KB ctor –Nonvolatile configuration locking –Password protection
–Hardware write protection: nonvolatile bits (BP[3:0] and TB) define protected area size –Program/era protection during power-up –CRC detects accidental changes to raw data •
Electronic signature
–JEDEC-standard 3-byte signature (BA21h)
–Extended device ID: two additional bytes identify device factory options •
JESD47H-compliant
–Minimum 100,000 ERASE cycles per ctor –Data retention: 20 years (TYP)
Options
Marking
•Voltage – 2.7–3.6V L •Density –1Gb
01G •Device stacking – 2 die stacked B •Device generation B •Die revision
B •Pin configuration –HOLD#
1–RESET and HOLD#8•Sector Size –64KB
E •Packages – JEDEC-standard, RoHS-compliant
–24-ball T-PBGA 05/6mm x 8mm (TBGA24)
12–16-pin SOP2, 300 mils (SO16W,SO16-Wide, SOIC-16)
SF –W-PDFN-8 8mm x 6mm (MLP8 8mm x 6mm)
W9•Security features –Standard curity 0•Special options –Standard S –Automotive
A •Operating temperature range –From –40°C to +85°C IT –From –40°C to +105°C AT –From –40°C to +125°C
UT
找Memory 、FPGA 、二三极管、连接器、模块、
光耦、电容电阻、单片机、处理器、晶振、传感器、 滤波器，
上深圳市美光存储技术有限公司
Part Number Ordering
Micron Serial NOR Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog arch at To compare features and sp
ecifications by device type,visit /products. Contact the factory for devices not found.Figure 1: Part Number Ordering Information
Production Status Blank = Production
ES = Engineering samples QS = Qualification samples Operating Temperature IT = –40°C to +85°C AT = –40°C to +105°C UT = –40°C to +125°C
Special Options S = Standard
A = Automotive grade AEC-Q100Security Features
0 = Standard default curity
Package Codes
12 = 24-ball T-PBGA, 05/6 x 8mm (5 x 5 array)14 = 24-ball T-PBGA, 05/6 x 8mm (4 x 6 array)SC = 8-pin SOP2, 150 mils SE = 8-pin SOP2, 208 mils SF = 16-pin SOP2, 300 mils W7 = 8-pin W-PDFN, 6 x 5mm W9 = 8-pin W-PDFN, 8 x 6mm 5x = WLCSP package 1
Sector size
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E = 64KB ctors, 4KB and 32KB subctors
Micron Technology Part Family 25Q = SPI NOR Voltage L = 2.7–3.6V U = 1.7–2.0V Density爬行比赛
064 = 64Mb (8MB)128 = 128Mb (16MB)256 = 256Mb (32MB)512 = 512Mb (64MB)01G = 1Gb (128MB)02G = 2Gb (256MB)Stack
A = 1 die/1 S#
B = 2 die/1 S#
C = 4 die/1 S#Device Generation B = 2nd generation Die Revision A = Rev. A B = Rev. B
Pin Configuration Option 1 = HOLD# pin 3 = RESET# pin
8 = RESET# and HOLD# pin
MT 25Q L
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A BA
1
E
所有节日
SF IT
-S
ES
Note: 1.WLCSP package codes, package size, and availability are density-specific. Contact the factory for availability.
Device Description
The MT25Q is a high-performance multiple input/output rial Flash memory device. It
features a high-speed SPI-compatible bus interface, execute-in-place (XIP) functionali-
ty, advanced write protection mechanisms, and extended address access. Innovative,
high-performance, dual and quad input/output commands enable double or quadru-
ple the transfer bandwidth for READ and PROGRAM operations.
Figure 2: Block Diagram
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Note: 1.Each page of memory can be individually programmed, but the device is not page-eras-
able.
1Gb, 3V Multiple I/O Serial Flash Memory
Memory Map – 1Gb Density
1Gb, 3V Multiple I/O Serial Flash Memory
Status Register Status Register
Status register bits can be read from or written to using READ STATUS REGISTER or
WRITE STATUS REGISTER commands, respectively. When the status register enable/
压缩文件夹错误disable bit (bit 7) is t to 1 and W# is driven LOW, the status register nonvolatile bits
become read-only and the WRITE STATUS REGISTER operation will not execute. The
only way to exit this hardware-protected mode is to drive W# HIGH.
