2002 Microchip Technology Inc.
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DS39025F-page 1
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PIC16F87X
This document includes the programming specifications for the following devices:
1.0
PROGRAMMING THE PIC16F87X
The PIC16F87X is programmed using a rial method.The Serial mode will allow the PIC16F87X to be pro-grammed while in the ur’s system. This allows for incread design flexibility. This programming specifi-cation applies to PIC16F87X devices in all packages.
1.1
Programming Algorithm Requirements
The programming algorithm ud depends on the operating voltage (V DD ) of the PIC16F87X device.Algorithm 1 is designed for a V DD range of 2.2V ≤V DD <5.5V. Algorithm 2 is for a range of
4.5V ≤V DD ≤5.5V. Either algorithm can be ud with the two available programming entry methods. The first method follows the normal Microchip Programming mode entry of applying a V PP voltage of 13V ± .5V. The cond method, called Low Voltage ICSP TM or LVP for short, applies V DD to MCLR and us the I/O pin RB3to enter Programming mode. When RB3 is driven to V DD from ground, the PIC16F87X device enters Programming mode.
1.2Programming Mode
The Programming mode for the PIC16F87X allows pro-gramming of ur program memory, data memory, spe-cial locations ud for ID, and the configuration word.
创新者的窘境•PIC16F870•PIC16F874•PIC16F871•PIC16F876•PIC16F872•PIC16F877
•PIC16F873
EEPROM Memory Programming Specification
PIC16F87X
DS39025F-page 2
2002 Microchip Technology Inc.
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F87X
Pin Name During Programming
Function Pin Type
Pin Description
RB3PGM I Low voltage ICSP programming input if LVP configuration bit equals 1RB6CLOCK I Clock input RB7DATA I/O Data input/output MCLR V TEST MODE
P*Program Mode Select V DD V DD P Power Supply V SS
V SS
P
Ground
Legend:I = Input, O = Output, P = Power
*In the PIC16F87X, the programming high voltage is internally generated. To activate the Programming mode, high voltage needs to be applied to the MCLR input. Since the MCLR is ud for a level source, this means that MCLR does not draw any significant current.
PIC16F87X
2.0PROGRAM MODE ENTRY
2.1Ur Program Memory Map
The ur memory space extends from 0x0000 to 0x1FFF (8K). In Programming mode, the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x1FFF) being ur program memory and the cond half (0x2000-0x3FFF) being configuration memory. The PC will increment from 0x0000 to 0x1FFF and wrap to 0x0000, 0x2000 to 0x3FFF and wrap around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a ‘1’, thus always pointing to the configuration memory. The only way to point to ur program mem-ory is to ret the part and re-enter Program/Verify mode, as described in Section2.4.
In the configuration memory space, 0x2000-0x200F are physically implemented. However, only locat
退避三舍意思ions 0x2000 through 0x2007 are available. Other locations are rerved. Locations beyond 0x200F will physically access ur memory (e Figure2-1).
2.2Data EEPROM Memory
The EEPROM data memory space is a parate block of high endurance memory that the ur access using a special quence of instructions. The amount of data EEPROM memory depends on the device and is shown below in number of bytes.The contents of data EEPROM memory have the capa-bility to be embedded into the HEX file.
The programmer should be able to read data EEPROM information from a HEX file and converly (as an option), write data EEPROM contents to a HEX file, along with program memory information and configura-tion bit information.
The 256 data memory locations are logically mapped starting at address 0x2100. The format for data mem-ory storage is one data byte per address location, LSB aligned.
2.3ID Locations
A ur may store identification information (ID) in four ID locations. The ID locations are mapped in [
0x2000 : 0x2003]. It is recommended that the ur u only the four Least Significant bits of each ID location. In some devices, the ID locations read out in an unscrambled fashion after code protection is enabled. For the devices, it is recommended that ID location is written as “11 1111 1000 bbbb” where ‘bbbb’ is ID information. In other devices, the ID locations read out normally, even after code protection. To understand how the devices behave, refer to Table5-1.
To understand the scrambling mechanism after code protection, refer to Section4.0.
Device# of Bytes
PIC16F87064
一针见血的近义词
PIC16F87164
PIC16F87264
PIC16F873128
PIC16F874128
PIC16F876256
PIC16F877256
2002 Microchip Technology Inc.DS39025F-page 3
惜时古诗PIC16F87X
DS39025F-page 4 2002 Microchip Technology Inc.
PIC16F87X
2.4Program/Verify Mode
The Program/Verify mode is entered by holding pins RB6 and RB7 low, while raising MCLR pin from V IL to V IHH (high voltage). In this mode, the state of the RB3 pin does not effect programming. Low voltage ICSP Programming mode is entered by raising RB3 from V IL to V DD and then applying V DD to MCLR. Once in this mode, the ur program memory and the configuration memory can be accesd and programmed in rial fashion. The mode of operation is rial, and the mem-ory that is accesd is the ur program memory. RB6 and RB7 are Schmitt Trigger Inputs in this mode.
The quence that enters the device into the Program-ming/Verify mode places all other logic into the RESET state (the MCLR pin was initially at V IL). This means that all I/O are in the RESET state (high impedance inputs).
The normal quence for programming is to u the load data command to t a value to be written at the lected address. Issue the begin programming com-mand followed by read data command to verify, and then increment the address.
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A device RESET will clear the PC and t the address to 0. The “increment address” command will increment the PC. The “load configuration” command will t the PC to 0x2000. The available commands are shown in Table2-2.
2.4.1LOW VOLTAGE ICSP
PROGRAMMING MODE
Low voltage ICSP Programming mode allows a PIC16F87X device to be programmed using V DD only. However, when this mode is enabled by a configuration bit (LVP), the PIC16F87X device dedicates RB3 to control entry/exit into Programming mode.
When LVP bit is t to ‘1’, the low voltage ICSP pro-gramming entry is enabled. Since the LVP configura-tion bit allows low voltage ICSP programming entry in its erad state, an erad device will have the LVP bit enabled at the factory. While LVP is ‘1’, RB3 is dedi-cated to low voltage ICSP programming. Bring RB3 to V DD and then MCLR to V DD to enter programming mode. All other specifications for high voltage ICSP™apply.
To disable low voltage ICSP mode, the LVP bit must be programmed to ‘0’. This must be done while
entered with High Voltage Entry mode (LVP bit = 1). RB3 is now a general purpo I/O pin.2.4.2SERIAL PROGRAM/VERIFY
OPERATION
The RB6 pin is ud as a clock input pin, and the RB7 pin is ud for entering command bits and data input/output during rial operation. To input a com-mand, the clock pin (RB6) is cycled six times. Each command bit is latched on the falling edge of the clock, with the Least Significant bit (LSb) of the command being input first. The data on pin RB7 is required to have a minimum tup and hold time (e AC/DC specifications), with respect to the falling edge of the clock. Commands that have data associated with them (read and load) are specified to have a minimum delay of 1 µs between the command and the data. After this delay, the clock pin is cycled 16 times with the first cycle being a START bit and the last cycle being a STOP bit. Data is also input and output LSb first.
Therefore, during a read operation, the LSb will be transmitted onto pin RB7 on the rising edge of the c-ond cycle, and during a load operation, the LSb will be latched on the falling edge of the cond cycle. A min-imum 1 µs delay is also specified between concutive commands.
All commands are transmitted LSb first. Data words are also transmitted LSb first. The data is trans
mitted on the rising edge and latched on the falling edge of the clock. To allow for decoding of commands and reversal of data pin configuration, a time paration of at least 1µs is required between a command and a data word (or another command).
The commands that are available are:
2.4.2.1Load Configuration
After receiving this command, the program counter (PC) will be t to 0x2000. By then applying 16 cycles to the clock pin, the chip will load 14-bits in a “data word,” as described above, to be programmed into the configuration memory. A description of the memory mapping schemes of the program memory for normal operation and Configuration mode operation is shown in Figure2-1. After the configuration memory is entered, the only way to get back to the ur program memory is to exit the Program/Verify Test mode by taking MCLR low (V IL).
2.4.2.2Load Data for Program Memory After receiving this command, the chip will load in a 14-bit “data word” when 16 cycles are applied, as described previously. A timing diagram for the load data command is shown in Figure6-1.
Note:The OSC must not have 72 osc clocks
while the device MCLR is between V IL and
V IHH.
2002 Microchip Technology Inc.DS39025F-page 5lo名词
PIC16F87X
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2002 Microchip Technology Inc.
2.4.2.3
Load Data for Data Memory
After receiving this command, the chip will load in a 14-bit “data word ” when 16 cycles are applied. How-ever, the data memory is only 8-bits wide, and thus,only the first 8-bits of data after the START bit will be programmed into the data memory. It is still necessary to cycle the clock the full 16 cycles in order to allow the internal circuitry to ret properly. The data memory contains up to 256 bytes. If the device is code pro-tected, the data is read as all zeros.
2.4.2.4Read Data from Program Memory
After receiving this command, the chip will transmit data bits out of the program memory (ur or configu-ration) currently accesd, starting with the cond ris-ing edge of the clock input. The RB7 pin will go into Output mode on the cond rising clock edge, and it will revert back to Input mode (hi-impedance) after the 16th rising edge. A timing diagram of this command is shown in Figure 6-2.
2.4.2.5Read Data from Data Memory
After receiving this command, the chip will transmit data bits out of the data memory starting with the c-ond rising edge of the clock input. The RB7 pin will go into Output mode on the cond rising edge, and it will revert back to Input mode (hi-impedance) after the 16th rising edge. As previously stated, the data memory is 8-bits wide, and therefore, only the first 8-bits that are output are actual data.
2.4.2.6
Increment Address
The PC is incremented when this command is received. A timing diagram of this command is shown
in Figure 6-3.
2.4.2.7Begin Era/Program Cycle
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A load command must be given before every begin programming command. Programming of the appro-priate memory (test program memory, ur program memory or data memory) will begin after this command is received and decoded. An internal timing mechanism executes an era before write. The ur must allow for both era and programming cycle times for program-ming to complete. No “end programming ” command is required.
2.4.2.8
Begin Programming
A load command must be given before every begin programming command. Programming of the appro-priate memory (test program memory, ur program memory or data memory) will begin after this command is received and decoded. An internal timing mechanism executes a write. The ur must allow for program cycle time for programming to complete. No “end pro-gramming ” command is required.
This command is similar to the ERASE/PROGRAM CYCLE command, except that a word era is not done. It is recommended that a bulk era be per-formed before starting a ries of programming only cycles.
Note:
The Begin Program operation must take place at 4.5 to 5.5 V DD range.
TABLE 2-2:COMMAND MAPPING FOR PIC16F87X
Command
Mapping (MSB … LSB)
Data Voltage Range Load Configuration
X X 00000, data (14), 0 2.2V - 5.5V Load Data for Program Memory X X 00100, data (14), 0 2.2V - 5.5V Read Data from Program Memory X X 01000, data (14), 0
2.2V - 5.5V Increment Address
X X 0110 2.2V - 5.5V Begin Era Programming Cycle 001000
2.2V - 5.5V Begin Programming Only Cycle 011000 4.5V - 5.5V Load Data for Data Memory X X 00110, data (14), 0 2.2V - 5.5V Read Data from Data Memory X X 01010, data (14), 0 2.2V - 5.5V Bulk Era Setup1000001 4.5V - 5.5V Bulk Era Setup2
1
1
1
4.5V -
5.5V
