High-speed CMOS Image Sensor for High-throughput Lensless
Microfluidic Imaging System
Mei Yan*a, Xiwei Huang a, Qixiang Jia a, Revanth Nadipalli a, Tongxi Wang a, Yang Shang a ,
Hao Yu a , Minkyu Je b, Kiatng Yeo a
a Nanyang Technological University, 50 Nanyang Ave, Singapore 639798
b Institute of Microelectronics, 11 Science Park Road, Singapore 117685
ABSTRACT
The integration of CMOS image nsor and microfluidics becomes a promising technology for point-of-care (POC) diagnosis. However, commercial image nsors usually have limited speed and low-light nsitivity. One high-speed and high-nsitivity CMOS image nsor chip is introduced in this paper, targeted for high-throughput microfluidic imaging system. Firstly, high speed image nsor architecture is introduced with design of column-parallel single-slope analog-to-digital converter (ADC) with digital correlated double sampling (CDS). The frame rate can be achieved to 2400 frames/cond (fps) with r
esolution of 128×96 for high-throughput microfluidic imaging. Secondly, the designed system has superior low-light nsitivity, which is achieved by large pixel size (10μm×10μm, 56% fill factor). Pixel peak signal-noi-ratio (SNR) reaches to 50dB with 10dB improvement compared to the commercial pixel (2.2μm×2.2μm). The degradation of pixel resolution is compensated by super-resolution image processing algorithm. By reconstructing single image with multiple low-resolution frames, we can equivalently achieve 2μm resolution with physical 10μm pixel. Thirdly, the system-on-chip (SoC) integration results in a real-time controlled intelligent imaging system without expensive data storage and time-consuming computer analysis. This initial nsor prototype with timing-control makes it possible to develop high-throughput lensless microfluidic imaging system for POC diagnosis.
Keywords: Point-of-Care, lensless microfluidic imaging system, high-throughput screening, high-speed image nor, super-resolution, intelligent system with real-time control
1.INTRODUCTION
Lensless microfluidic imaging system has become a promising technology for point-of-care (POC) diagnosis. It is the integration of CMOS image nsor chip and microfluidic channel. Since there are 内表面
plenty of bio-samples in fluid form, the u of microfluidics has become an excellent means for transporting samples [1]. At the same time, the traditional bio-imaging system usually needs large optical lens to magnify the object. In microfluidic imaging system, the object is placed directly on the surface of CMOS image nsor chip to get rid of bulky optical lens. As such, it leads to significant area and cost savings for POC applications. The first optofluidic microscope system is explored in [2, 3]. The sample flows in the microfluidic channel, then image is captured continuously by commercial CMOS image nsor chip, and data analysis is performed off-chip. Such invention has shown potential for developing portable, low-power and low-cost microscope for POC diagnosis. However, the primary limitation is from the design of CMOS imager nsor such as limited speed and nsitivity without real-time control ability.
In this paper, we propo a microfluidic imaging platform for high-throughput POC diagnosis. Firstly, the high-speed image nsor is implemented with design of column-parallel single-slope ADC architecture and digital correlated double sampling (CDS) [4, 5]. The achieved frame rate reaches up to 2400fps with 128×96 resolution for high-throughput microfluidic imaging. Secondly, large pixel size (10um×10um, 56% fill factor) is designed to achieve superior low-light nsitivity. Pixel peak signal-noi-ratio (SNR) reaches to 50dB with 10dB improvement compared to commercial pixel (2.2μm×2.
2μm). The degradation of pixel resolution is compensated by super-resolution processing algorithm. By
reconstructing single image with multiple low-resolution frames, we can equivalently achieve 2μm resolution with 10μm physical pixel. Thirdly, the system-on-chip (SoC) integration results in a real-time controlled intelligent imaging system without expensive data storage and time-consuming computer analysis. As a result, our initial nsor prototype with timing-control makes it possible to develop lensless microfluidic imaging system for POC diagnosis.
The rest of this paper is organized as follows. In Section 2, we first introduce the basic concept of microfluidic imaging system. Then we describe the high-speed CMOS image nsor design in Section 3 and FPGA implementation of super-resolution imaging algorithm in Section 4. We prent the experiment results in Section 5 with conclusions in Section 6.
2.LENSLESS MICROFLUIDIC IMAGING SYSTEM
2.1Conventional microfluidic imaging system
A conventional imaging system usually consists of an objective lens, a big space for relaying the ima
ge, and an imaging lens to project the magnified image onto a human retina or a camera. In addition to its high implementation cost, traditional imaging system is difficult to miniaturize due to the bulky optical lens. Lensless microfluidic imaging system is bad on the principle of contact imaging [6], where object can be recognized as long as it is clo enough to the nsor. The abnce of optical elements implies the possibility of compact implementation in a lab-on-chip fashion.
Figure 1. Conventional microfluidic imaging system [2, 3].
As shown in Figure 1, conventional microfluidic imaging systems usually include the following parts. 1) Microfluidic chip: the microfluidic chip is routed right over the pixel array of the CMOS image nsor with samples delivered through internal microfluidic channels. The inlet and outlet of the microfluidic channels are fabricated at both sides on top of the microfluidic chip. The channel dimension depends on the sample size, which usually has the width around 50μm and height around 20μm. It is made by poly-dimenthyl-siloxane (PDMS) which are cast from silicon wafer molds. This material has low operating cost and easy to maintain. The fluids are propelled and controlled by the syringe pump from outside. Due to their small volume, the microfluidic channels can greatly reduce the reagent u. 2) CMOS image nsor chip: when the specimens flow through the microfluidic channels, CMOS image nsor chip captures a quence of image frames. Since the samples are m
oving with the fluid, the overall throughput of system is determined by the sample flowing speed and image
nsor frame rate. The flow speed usually can be adjusted by the flow control mechanism, such as pressure or electric field. Therefore, the ultimate throughput limitation comes from the speed of CMOS image nsor. The off-the-shelf commercial CMOS image nsor chip is usually designed for 30fps, way behind the high throughput system requirement. As a result, the conventional microfluidic imaging system only has limited application, such as microscope [2]. 3) FPGA chip : pixel size of image nsor chip is another important factor which will affect the system performance of resolution. This non-magnifying direct-imaging system has limited resolution of pixel size (μm). Thanks to advanced imaging analysis algorithm, a multi-frame super-resolution (SR) approach is implemented with FPGA to improve the resolution. The working principle of SR is combining information from multiple sub-pixel-shifted low-resolution (LR) images to create a single high-resolution (HR) image. Although FPGA approach improves the processing speed veral orders compared to software approach (for example, to obtain one HR frame, FPGA needs 1 ms, while C code or MATLAB needs 1s), it still requires certain time to transfer the data off-chip and store multiple frames for imaging processing, which limits its speed for high-throughput application.
2.2
Propod real-time on-chip high-throughput microfluidic imaging system
To overcome the speed limitation of conventional microfluidic imaging system, we propo a single chip solution for high-throughput microfluidic imaging system as shown in Figure 2. The primary contribution of this paper is the design of one specified high-speed CMOS image nsor. Image quality is improved by large pixel with better low-light nsitivity. Column-parallel readout architecture with digital correlated double sampling (CDS) technique [4, 5] is implemented to reach more than 2400fps frame rate. Moreover, single-frame super-resolution algorithm is implemented on-chip for real-time system control, which takes in the image information row by row, and process immediately. On the contrary, the previous multi-frame super-resolution approaches [3, 7, 8] require storing veral LR frames to achieve one HR frame, which has limited speed. Finally, to further increa the processing throughput of the microfluidic imaging system, the microfluidic chip can be fabricated with multiple parallel channels instead of one single channel [9]. As a result, when the single-frame super-resolution approach is implemented on-chip, and leveraged with CMOS image nsor column-parallel readout, one can process the image instantly with high-speed yet high-nsitivity. As soon as one frame of image is read out from nsor, the super-resolution processing h
铁扫as already finished. There is no need to store and wait till different frames of image are output. In other words, the captured images can be instantly procesd and real-time control can be conducted. The details will be discusd in the following ctions.
Inlet Outlet
生蚝保存
医养结合养老实施方案Microfluidic Flow Specimen CMOS Image Sensor
(c)CMOS Image Sensor Chip Package
(b)
(a)
Figure 2. Lensless microfluidic imaging system structure: (a) Propod integrated lensless microfluidic imaging system diagram; (b) multichannel microfluidic chip [9]; (c) high-speed CMOS image nsor with SoC implemented single-frame super-resolution algorithm.
3.HIGH-SPEED CMOS IMAGE SENSOR DESIGN
3.1Chip overview
As the block diagram shows in Figure 3 (a), the high-speed CMOS image nsor design employs the column-parallel readout architecture. The nsor consists of a 128(H) × 96(V) active pixel array. In the pixel parallel readout path, each column has column amplifier, 10-bit single-slope analog-to-digital convertor (SS-ADC) and SRAM memory. The row decoder and row driver drive out the pixel signals in row by row mode, which coordinates with the single-frame super-resolution algorithm to be introduced in the next ction. The IDAC provides the biasing currents for all the on-chip components. The SREG is the static register ud during the initialization period to generate static control signals for all the on-chip components. The layout corresponding to the block diagram is shown in Figure 3(b).
(a) (b)
Figure 3. (a) Block diagram of the CMOS image nsor; (b) Top layout of the taped out CMOS image nsor.
3.2High nsitivity pixel
属金的颜色
For bio-medical imaging applications, since most testing condition is under low-light circumstance, high-nsitivity becomes one important factor in the design. However, noisy 3T pixel structure is commonly implemented due to the limitation of standard mixed-signal process (Global Foundry), which requires high SNR especially for pixel design. Here we implement 10μm×10μm pixel size with a fill factor of 56%, which is optimized for better low-light nsitivity. Due to this large pixel size, the pixel peak SNR reaches 50dB which is at least 10dB larger than the commercial pixels (2.2μm×2.2μm). The large pixel size also shows special advantage in the reduction of pixel integration time, which further leads to higher frame rate. However, there is a tradeoff between spatial resolution and light nsitivity: large pixel reduces the resolution of the captured image but increas the nsitivity [10]. In our design, we apply image processing technique such as super-
普通的一天
resolution algorithm to improve the spatial resolution. When microfluidic flow delivers samples across the image nsor surface, the multi-frame LR image quence is procesd with super-resol
ution algorithm to reconstruct single image with higher resolution. As a result, the tradeoff between nsitivity and resolution can be optimized. The details of the super-resolution algorithm and implementation will be discusd in the next ction.
3.3Column parallel ADC
常伴你左右Overall, there are three major architectures in CMOS image nsor design: global ADC readout, column-parallel ADC readout and pixel-level ADC readout. Among the architectures, column-parallel ADC architecture has been widely ud to achieve high-speed performance. With column-parallel readout architecture, all the pixel data can be read out concurrently, without the need to wait column-by-column when compared with the global ADC readout. Thus the nsor can reach high frame rate. It also provides better area efficiency compared to pixel-level ADC readout, while providing more image processing possibilities. Moreover, among different ADC topologies, the single-slope ADC is gaining more popularity becau it shows advantages on both power consumption and area efficiency.
Figure 4. Schematic diagram of the single-slope column ADC and pixel signal readout path.
As shown in Figure 4, pixel output is first amplified by a switch-capacitor type column amplifier. The main amplifier ud is Cascode with differential input and single output. The input capacitor of the column amplifier is fixed at 800fF and the
>现金奖励
