An Improved CMOS Ring Oscillator PLL with
Less than 4ps RMS Accumulated Jitter
Stephen Williams, Hugh Thompson, Michael Hufford, Eric Naviasky
Cadence Design Services, 6210 Old Dobbin Lane, Suite 100, Columbia, Maryland 21045, USA
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Abstract This paper describes a low jitter pha-locked-loop (PLL) with a 4th order control path, and a dual control voltage ring oscillator. Near constant voltage controlled oscillator
(VCO) gain over process variations, in addition to compensa-tion for feedback ratio variation, allows improved control of the PLL bandwidth. The PLL exhibits improved noi im-munity with a wide (5:1) VCO frequency range, without the
need for band switching or calibration routines. This PLL is fabricated in a 0.18µm CMOS logic process and exhibits <4ps rms accumulated jitter.
I. Introduction
A conventional 3rd order PLL architecture consists
of a pha-frequency detector (PFD), a charge pump (CP), a 2nd order loop filter, a VCO, and a feedback divider as shown
in Fig. 1. The gain of the PFD and CP (K PFD ) is proportional
to the charge pump maximum output current I CP . K LF is the
transfer function of the loop filter and is equal to the imped-ance of the filter (1).
)
(1)(j ωj ω)1j ω()j ω(2121ττ
C C K LF +⋅+⋅⋅+⋅=
(1) where: 111τ
C R ⋅=;)/(22121τ
τC C C +⋅=
K VCO is the voltage-to-frequency gain of the VCO in units of Hz/V. The feedback divider has a gain of 1/M , where M is the modulus of the divider. This results in an open loop gain equation given by (2). M
C C I K H CP
VCO ⋅+⋅+⋅⋅⋅⋅+⋅=)(1)(j ω)j ω()1j ω()j ω(21221τ
τ (2) A plot of the open loop gain equation is shown in Fig. 2,
where F 1=1/(2π·τ1) and F 2=1/(2π·τ2). A disadvantage of this type of PLL architecture us-ing a CMOS inverter ring oscillator is that K VCO is not typi-cally well controlled over process variations. In addition, K VCO in a conventional ring oscillator is non-linear with fre-quency which caus K VCO variation with changes in M for a fixed reference frequency (F REF ). Having K VCO variation can lead to a PLL bandwidth that is not well controlled and de-grade the jitter performance of the PLL [1].
Another disadvantage of this architecture is that in order to span a wide range of VCO frequencies (F VCO ), K VCO needs to be large due to a limited control voltage range. A
large K VCO increas the PLL’s nsitivity to I CP noi, loop filter noi, and ripple cau by charge pump mismatches [2].
φVCO φCP PFD I K =VCO K ⋅⎟⎞
⎜⎛2π F 1
F 2)
(ωj H f Fig. 2: Open loop transfer curve of a conventional 3rd order PLL This problem becomes wor as supply ranges decrea with
smaller process technologies, and limit the control voltage
range further. This paper prents improvements to the conven-tional PLL design to correct the di
sadvantages. The im-provements consisted of changing to a 4th order PLL architec-ture, and using a dual control VCO with feedback ratio com-pensation. II. 4th Order, Dual Control Path PLL Architecture The architecture described in this paper is shown in Fig. 3. This architecture us an additional 4th
order control
path to add a coar tuning control with a bandwidth much lower than the PLL bandwidth. This was implemented with a g m -C stage which integrates the difference of internal loop filter voltage on C 1 and voltage reference V REF . The transfer function of the gm-C stage is shown in (3). g m is the trans-conductance of the amplifier, g OUT is the output impedance,
and OUT g C /33τ
=. )
j ω1()
/()j ω(3τ
⋅+=OUT m GMC g g K (3) The voltage on C 1 of the loop filter (K LFC1) can be found by using K LF from (1) to arrive at (4).
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φVCO
()VCOFINE K ⋅⎟⎟⎠⎞⎜⎜⎝⎛j ω2π()K ⋅⎟⎞⎜⎛2π
精彩英文()
1ω1
)j ω()j ω(11τ+⋅
时新=j K K LF LFC
)
香港自助旅游(1)(j ωj ω1)j ω(2121τ
C C K LFC +⋅+⋅⋅= (4) The total open loop transfer function (5) of the improved PLL can be en in Fig. 4, where F 3=1/(2πτ3). K VCOCOARSE is the voltage-to-frequency gain of the VCO’s V COARSE input, and K VCOFINE is the gain of the V FINE input.
()⎟⎟⎠
⎞
⎜⎜⎝⎛⋅⋅⋅⋅=M I K K K H CP VCOCOARSE GMC LFC )j ω()j ω()j ω()j ω(1 ()⎟⎟⎠
⎞
⎜⎜⎝⎛⋅⋅⋅+M I K K CP VCOFINE LF )j ω()j ω( ()()()⎟⎟⎟⎟⎠⎞⎜⎜⎜⎜⎝⎛⋅+⋅+⋅⋅+⋅⋅⋅⎟⎠⎞⎜⎝⎛=⋅M C C K I H VCOCOARSE g g CP out m 21322
1j ω1j ω)j ω()j ω(τ
τ ()()()⎟
萎的近义词⎟⎠⎞⎜⎜⎝⎛⋅+⋅+⋅⋅⋅⋅+⋅+M C C K I VCOFINE
CP 212211j ω)j ω(
1j ωττ (5) A point of interest is where the summed terms of (5) are equal. This point is shown in Fig. 4 as F 4. The K VCOCOARSE term should be adjusted so that F 4 < F 1, and so that the K VCO-COARSE path is not a significant factor in determining PLL pha margin or bandwidth. Details of the improved ring oscillator with V COARSE and V FINE controls required for this architecture is prented in ction III. III. Dual Control Voltage Ring Oscillator The improved ring oscillator has fine and coar tun-ing controls, and has a well controlled K VCOFINE that is ap-proximately linearly proportional to F VCO . A schematic of one of five ring stages can be en in Fig. 5. The supply voltage of the VCO (V REG ) is regulated from a 1.8V supply. A common source PMOS device (M1) provides a high gain V COARSE tuning control. A low gain V FINE input is connected to an NMOS inversion mode capacitor (C V ) ud as a )
(ωj H f
Fig. 4: Open loop transfer function of the 4 order, dual control path PLL
V
V
FINE
varactor to adjust the speed of the ring. Two stacked diode connected NMOS devices (M3) and (M4) are ud as a clamp
to limit the oscillation’s amplitude dependence on V REG . This keeps the output ret time via M2 consistent and improves power supply noi nsitivity. Some additional load capaci-tance (C L ) is added to help minimize the VCO’s tuning curve dependence on parasitic capacitances. A sixth stage without
C L and C V is ud for conversion to CMOS logic levels.
One important aspect of this improved VCO design is that K VCOFINE is determined by the ratio of (∆C V ):(C L ), as-suming that the capacitance on the “OUT” node of Fig. 5 is
dominated by C L . Since both C V and C L are NMOS capaci-tors, their ratio will be well controlled over process variations.
Another important design aspect is that K VCOFINE is
approximately linearly proportional to F VCO , and thus propor-tional to M for constant F REF . This means that (K VCOFINE / M ) from (5) is constant for changes in M . This can be shown by using the approximation for a single stage of the ring oscilla-tor as shown in Fig. 6. The comparator models the NMOS switch that rets C L (M2 in Fig. 5) at voltage V TH .
FINEMAX
FINE V V ≤≤VMAX V C C 0F ≤≤OUT
The slew rate of the output voltage is given by (8).
)(V L TH C C i
t V +=∆ (8) Assuming an n stage VCO running at F VCO , for a single stage VCO F n t ⋅⋅=∆2)/(1.
()REF TH V L VCO F M V n C C i
i F ⋅=⋅⋅⋅+=2)( (9) ()TH V L REF V n C C F M i ⋅⋅⋅+⋅⋅=2 (10)
=∆∆=
FINE VCO VCOFINE V i F i K )
()( ()()
FINEMIN FINEMAX TH VMAX L TH L
V V V n C C i
V n C i −⎟⎟⎠⎞⎜⎜⎝⎛⋅⋅⋅+−⎟⎟⎠⎞⎜⎜⎝⎛⋅⋅⋅=22 ()
FINEMIN FINEMAX C C TH L V V V n C i L VMAX −⎟⎟⎟⎠⎞⎜⎜⎜
⎝⎛+−⋅⋅⋅⋅=1112 Using the small signal approximation ()()εε−≅+11/1:
()()
FINEMIN FINEMAX TH L VMAX VCOFINE V V i V C n C i K −⋅⎟
⎟⎠⎞⎜⎜⎝
⎛⋅⋅⋅≅22)( (11)
Now combining (10) into (11),
()
()FINEMIN VINEMAX L REF VMAX C C VCOFINE V V C F C
M
K L
VMAX −⎟⎟⎟⎠
⎞⎜⎜⎜⎝⎛⋅⋅+≅
1 (12) Looking at (12) we can e that (K VCOFINE /M ) is ap-proximately a constant assuming F REF is constant.
IV. PLL Architecture Advantages
A.. Well Controlled PLL Bandwidth
Assume that the K VCOCOARSE variation has a negligi-ble impact on PLL bandwidth and pha margin, as men-tioned in Section II. It was shown that K VCOFINE can be made dependant on the (∆C V ):(C L ) ratio which is well controlled over process corners. In addition it was shown that,
(K VCOFINE )/(M ) is approximately constant for changing values of M . Neglecting the K VCOCOARSE term in (5) becau of low bandwidth in this path, the PLL bandwidth is well controlled
due to reduced K VCOFINE variation with process and due to a
constant (K VCOFINE )/(M ) term.
B.. Simplified Charge Pump Design Another advantage to this architecture is that the de-sign of the charge pump is simpler. In the standard PLL ar-chitecture, the charge pump needs a wide output voltage
compliance range to be able to lock to a wide range of fre-quencies. This can cau charge pump offt and result in
reference spurs on the output of the VCO [3]. Using a g m stage with a voltage reference V REF , f
orces the output of the
charge pump to V REF under locked conditions. This allows
the charge pump output to be t to a known voltage during locked conditions. Output voltage compliance constraints are
moved to the g m
amplifier which can be easily designed to
春天有关的词语swing rail to rail..
C.. Improved Jitter Performance for wide F VCO Range
In this PLL architecture, each VCO control voltage input can have a different gain. The noi advantage to mak-ing K VCOFINE < K VCOCOARSE is that the gain in the wider band-width V FINE path can be reduced. This reduces nsitivity to
both random and deterministic noi. Since charge pump random noi is proportional to CP I , PLL noi is improved by increasing I CP and reducing K VCOFINE by the same factor for a given PLL bandwidth. A clod loop random noi
analysis is shown in Fig. 7. Having a low VCO gain in the wider bandwidth path also improves rejection of supply noi
[4]. A large K VCOCOARSE in the lower bandwidth path still al-lows for a wide F VCO range without the need for band switch-ing or calibration.
Fig. 7: PLL clod loop random noi analysis bad on simulated pha noi data for REFCLK, VCO, R 1, Charge Pump, g m , and feedback divider
IV. Experimental Results
The described PLL was implemented in a system with a noi supply environment from both lf-induced syn-chronous noi, and asynchronous noi from a switching power supply operating at approximately 120kHz. Nominal PLL parameters are shown in Table I. Measurements were taken via a test port with a test clock equal to (⅓)·F VCO . M was t to 10 so that reference spurs coupled onto the noisy test output could be distinguished from reference spurs on the VCO output (Fig. 8). Measured spur levels need to be ad-justed by 20·log 10(3)=9.5dB to account for the freque
ncy di-vision. Adjusted reference spur levels at (7/3)·F REF and (10/3)·F REF are -57.5dB and -66.7dB Respectively. The spurs at multiples of F REF are picked up on the noisy test output. It has been shown that in a PLL jitter accumulates for a time equal to the time constant of the PLL bandwidth (τL ) [5]. For the improved PLL design prented, the ob-rved accumulated jitter was <4ps rms measured at τL =177ns. Table II. shows the PLL performance summary.
Fundamental at (10/3) F REF
Reference Spur at (7/3) F REF and (13/3) F REF
3 F REF
4 F R EF
Test output noi at
3 F REF and
4 F REF
Fig. 8: Measured spurious on PLL test output
朱泾镇
TABLE II
PLL PERFORMANCE SUMMARY
@ F VCO =270MHz
Reference Spurs <-57dB F VCO Range 100MHz – 500MHz Supply Voltage 1.8V
公务员什么意思Power 24.3mW Technology 0.18µm CMOS Logic Process Silicon Area 160e3 µm 2
Fig. 9: Die Micrograph showing improved PLL
Fig. 10: Plot with dimensions and PLL component placement
References
[1] K. Minami, M. Fukaishi, M.i Mizuno, H. Onishi, K. Noda, et. al., “A
0.10µm CMOS, 1.2V, 2Ghz Pha-Locked Loop with Gain Compensa-tion VCO,” IEEE Custom Integrated Circuits Conference, 2001, pp. 213-214.
[2] L. Sun, D. Nelson, “A 1.0V GHz Range 0.13µm CMOS Frequency
Synthesizer,” IEEE Custom Integrated Circuits Conference, 2001, p. 327.
[3] J. Craninckx, M. S. J. Steyaert, “A Fully Integrated CMOS DCS-1800
Frequency Synthesizer,” IEEE Journal of Solid State Circuits , vol. 33, pp. 2056-2057, Dec. 1998.
[4] W. B. Wilson, U. Moon, K. Lakshmikumar, and L. Dai, “A CMOS
Self-calibrating Frequency Synthesizer,” IEEE Journal of Solid State Circuits , Vol. 35, pp.1437-1441, Oct. 2000.
[5] John A. McNiell, “Jitter in Ring Oscillators,” IEEE Journal of Solid
State Circuits , Vol. 32, pp.871-872, June 1997.
TABLE I
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NOMINAL LOOP PARAMETERS
Parameter Value Parameter Value K PFD 193µA M 10 K VCOCOARSE 866MHz/V Bandwidth 900kHz
K VCOFINE 15MHz/V Pha Margin 70º
g m 0.582µS F 1 139kHz g OUT 5.8 µS F 2 4.58MHz C 3 150pF F 3 6kHz R 1 22.4k Ω F 4 34.6kHz C 1 51.2pF F REF 27MHz C 2 1.6pF F VCO 270MHz
