1
Contents
1.0 Introduction
2.0 Interface Overview
2.1 GPSI Interface 2.2 MII Interface 2.3 RMII Interface 2.4 GMII Interface
3.0 Interface Configuration
3.1 Port Operation Mode 3.2 Port Interface Mode
3.2.1 MDS10x, MVTX1100
3.2.1.1 XLink Interface (Port 8)3.2.2 MDS213
3.2.3 ZL5041x, MVTX260x & MVTX280x 3.2.4 ZL5040x
3.2.
4.1 Bi-directional Clock
4.0 Interface Connections
4.1 GPSI Ports
4.1.1 ZL5040x GPSI 4.2 MII Ports
4.2.1 ZL5040x MII 4.3 RMII Ports 4.4 GMII Ports
5.0 Layout Considerations
1.0 Introduction
This application note describes MAC-to-MAC connections for the Fast Ethernet (FE) ports and Gigabit Ethernet (GE) ports for Zarlink Ethernet Switch family, which eliminates the need for a PHY . This document will also cover some unique chip features,such as the ZL5040x bi-directional clocks,
which aid in MAC-to-MAC connections.
The document provides a generic solution for MAC-to-MAC connections, but will include some unique features that may only apply to a specific chipt.Readers of this document should be familiar with the applicable chipt datasheet before proceeding.
2.0 Interface Overview
2.1 GPSI Interface
The GPSI interface consists of a rial data path on both receive and transmit sides. From the MAC point of view, only transmit data (TXD) and transmit enable (TXEN) are outputs, the rest of the signals are inputs.This interface is meant to operate at 1/10M.
快乐星期五
July 2003
ZLAN-30
Ethernet Switch
MAC-to-MAC Connections
Application Note为伊憔悴
The GPSI MAC-to-MAC connection should be configured as full duplex mode operation. For this reason, both CRS and COL are not needed for the GPSI MAC-to-MAC connection
2.2 MII Interface
开心的事作文
The MII interface consists of a 4-bit wide data path on both receive and transmit sides. From the MAC point of view,only transmit data (TXD[3:0]) and transmit enable (TXEN) are outputs, the rest of the signals are inputs. This interface is meant to operate at 10/100M.
The MII MAC-to-MAC connection should be configured as full duplex mode operation. For this reason, both CRS and COL are not needed for the MII MAC-to-MAC connection.
GPSI Signal Name
MAC Signal Direction
Description Notes
TXD O Transmit Data Bits driven on rising edge of TXCLK)TXEN O Transmit Data Enable indicated valid TXD TXCLK I Transmit Clock 1MHz or 10MHz
RXD I Receive Data Bit driven on rising edge of RXCLK RXDV I Receive Data Valid indicated valid RXD RXCLK I Receive Clock 1MHz or 10MHz CRS I Carrier Sen active during tx/rx activity
COL
I
Collision Detected
asrted when collision detected in tx/rx path
Table 1 - GPSI Interface Description
MII Signal Name MAC Signal Direction工作述职ppt
Description Notes
TXD[3:0]O Transmit Data Bits [3:0]driven on rising edge of TXCLK TXEN O Transmit Data Enable in
dicated valid TXD[3:0]TXCLK I Transmit Clock 2.5 (10M) or 25MHz (100M)RXD[3:0]I Receive Data Bit [3:0]driven on rising edge of RXCLK RXDV I Receive Data Valid indicated valid RXD[3:0]RXCLK I Receive Clock 2.5MHz (10M) or 25MHz (100M)CRS I Carrier Sen active during tx/rx activity
COL
I
Collision Detected
asrted when collision detected in tx/rx path
Table 2 - MII Interface Description
2.3 RMII Interface
The RMII interface consists of a 2-bit wide data path on both receive and transmit sides. From the MAC point of view, only transmit data (TXD[1:0]) and transmit enable (TXEN) are outputs, the rest of the signals are inputs. This interface is meant to operate at 10/100M.
The RMII MAC-to-MAC connection should be configured as full duplex mode operation.
2.4 GMII Interface
The GMII interface consists of a 8-bit wide data path on both receive and transmit sides. From the MAC point of view, transmit data (TXD[7:0]), transmit enable (TXEN), transmit clock (TXCLK) and transmit error (TXER) are outputs, the rest of the signals are inputs. This interface is meant to operate at 1000M (1G).
The GMII MAC-to-MAC connection should be configured as 1G, full duplex mode operation. For this reason, both CRS and COL are not needed for the GMII MAC-to-MAC connection.
RMII Signal Name MAC Signal Direction
Description Notes
TXD[1:0]O Transmit Data Bits [3:0]driven on rising edge of TXCLK TXEN O Transmit Data Enable indicated valid TXD[3:0]RXD[1:0]I Receive Data Bit [3:0]driven on rising edge of RXCLK
CRS_DV I Carrier Sen and Receive Data Valid indicated valid RXD[1:0] and/or tx/rx activity M_CLK
I
Reference Clock
50MHz
Table 3 - RMII Interface Description
GMII Signal Name MAC Signal Direction
Description Notes
TXD[7:0]O Transmit Data Bits [3:0]driven on rising edge of TXCLK TXEN O Transmit Data Enable indicated valid TXD[7:0]
TXER O Transmit error indicated error during transmission TXCLK O Transmit Clock 125MHz多通风
RXD[7:0]I Receive Data Bit [3:0]driven on rising edge of RXCLK RXDV I Receive Data Valid indicated valid RXD[7:0]RXER I Receive error indicated error during reception RXCLK I Receive Clock 125MHz
CRS I Carrier Sen active during tx/rx activity
COL
I
Collision Detected
asrted when collision detected in tx/rx path
Table 4 - GMII Interface Description
3.0 Interface Configuration
3.1 Port Operation Mode
Configuration register ECR1Pn (for most chipts) is ud to lection the ports operation mode (speed/duplex/flow control). Below is an overview of applicable bits in this register (does not apply to MDS21x):
ECR1Pn
•Accesd by CPU and I²C (R/W)
Bit [0] 1 - Flow Control Off
0 - Flow Control On
田野调查法When Flow Control On:
•In half duplex mode, the MAC transmitter applies back pressure for flow control.
•In full duplex mode, the MAC transmitter nds Flow Control frames when necessary. The MAC receiver interprets and process incoming flow control frames. The Flow Control Frame
Received counter is incremented whenever a flow control is received.
When Flow Control Off:
•In half duplex mode, the MAC transmitter does not asrt flow control by nding flow control frame or jamming collision.
•In full duplex mode, the Mac transmitter does not nd flow control frames. The MAC receiver does not interpret or process the flow control frames. The Flow Control Frame Received
counter is not incremented.
Bit [1] 1 - Half Duplex - Only in 10/100 mode
0 - Full Duplex
Bit [2] 1 - 10Mbps
0 - 100Mbps
MDS10x, MVTX1100
Bit [3]0 - Enable Auto-Negotiation
This enables hardware state machine for auto-negotiation.
1 - Limited Disable Auto-Negotiation
This disables hardware state machine for speed auto-negotiation (u ECR1Pn[2:0] for
configuration). Hardware will still poll PHY for link status.
MVTX260x, MVTX280x, ZL5041x, ZL5040x
Bit [4:3]00 - Enable Auto-Negotiation
This enables hardware state machine for auto-negotiation.邓梦婷
01 - Limited Disable Auto-Negotiation
This disables hardware state machine for speed auto-negotiation (u ECR1Pn[2:0] for
configuration). Hardware will still poll PHY for link status.
10 - Force Link Down
Disable the port. Hardware does not talk to PHY.
11 - Force Link Up
The configuration in ECR1Pn[2:0] is ud for (speed/duplex/flow control) tup. Hardware does
not talk to PHY.
Table 5 - Port Operation Mode
To configure the Ethernet switch ports for specific GMII/RMII/MII/GPSI modes, either bootstrap pins or configuration registers are ud. The following ctions outline specific methods.
3.2 Port Interface Mode
3.2.1 MDS10x, MVTX1100
For the chipt, bootstrap pins are ud. Below is an overview:
Pin Name Description
L_A[17]Port 8
0 - GPSI
1 - MII
Table 6 - MDS10x Port Interface Mode
Pin Name Description
L_A[15]Ports 0-7
0 - GPSI
1 - RMII
L_A[17]Port 8
0 - GPSI
1 - MII
Table 7 - MVTX1100 Port Interface Mode
3.2.1.1 XLink Interface (Port 8)
A key feature that the MDS108/MVTX1100 chipt provides is the ability to increa port 8 MII connection from 100M to 400M if connected to another MDS108/MVTX1100 device. Refer to the XLink Interface Application Note (MSAN-216) for more information.
3.2.2 MDS213
For the MDS213, configuration register DCR2 is ud to lect the interface type (GMII/TBI) for the gigabit port. Below is an overview of applicable bits in this register.
DCR2
•CPU Address:7C8
•Accesd by CPU (R/W)
Bit[24]:SEL_PCS
0 - U external PCS (GMII)
1 - U internal PCS in the chip (TBI)
豆腐菜怎么做Table 8 - ZL5040x Port Interface Mode
