Features
•Fast Read Access Time – 90 ns
•5-volt Only Reprogramming
•Sector Program Operation
–Single Cycle Reprogram (Era and Program)
–2048 Sectors (256 Bytes/Sector)
–Internal Address and Data Latches for 256 Bytes
•Internal Program Control and Timer
•Hardware and Software Data Protection
•Two 16K Bytes Boot Blocks with Lockout
•Fast Sector Program Cycle Time – 10 ms
•DATA Polling for End of Program Detection
•Low Power Dissipation
–40 mA Active Current
–100 µA CMOS Standby Current
•Typical Endurance > 10,000 Cycles
•Single 5V ± 10% Supply
•Green (Pb/Halide-free) Packaging Option
1.Description
The AT29C040A is a 5-volt only in-system Flash Programmable and Erasable Read Only Memory (PEROM). Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology, the device offers access times up to 90 ns, and a low 220 mW power dissipation. When the device is delected, the CMOS standby current
is less than 100µA. The device endurance is such that any ctor can typically be written to in excess of 10,000 times. The programming algorithm is compatible with other devices in Atmel’s 5-volt only Flash family.
To allow for simple in-system reprogrammability, the AT29C040A does not require high input voltages for programming. Five-volt-only commands determine the opera-tion of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29C040A is performed on a ctor basis; 256 bytes of data are loaded into the device and then simultaneously programmed.
During a reprogram cycle, the address locations and 256 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically era the ctor and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected, a new access for a read or program can begin.
BDTIC /ATMEL
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2.Pin Configurations
2.132-lead PLCC Top View
2.232-lead TSOP Top View – Type 1
Pin Name Function A0 - A18Address CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7Data Inputs/Outputs NC
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No Connect
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3.Block Diagram
4.Device Operation
4.1
Read
The AT29C040A is accesd like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asrted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line con-trol gives designers flexibility in preventing bus contention.
4.2Byte Load
Byte loads are ud to enter the 256 bytes of a ctor to be programmed or the software codes for data protection. A byte load is performed by applying a low pul on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.
仁爱英语网4.3Program
The device is reprogrammed on a ctor basis. If a byte of data within a ctor is to be changed, data for the entire ctor must be loaded into the device. Any byte that is not loaded during the programming of its ctor will be erad to read FFH. Once the bytes of a ctor are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high to low transition on WE (or CE) within 150 μs of the low to high transition of WE (or CE) of the preceding byte. If a high to low transition is not detected within 150 μs of the last low to high transition, the load period will end and the internal programming period will start. A8 to A18 specify the ctor address. The ctor address must be valid during each
high to low transition of WE (or CE). A0 to A7 specify the byte address within the ctor. The bytes may be loaded in any order; quential loading is not required. Once a programming operation has been initiated, and for the duration of t WC , a read operation will effectively be a polling operation.
企业研究4.4Software Data Protection
A software controlled data protection feature is available on the AT29C040A. Once the software
protection is enabled a software algorithm must be issued to the device before a program may
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be performed. The software protection feature may be enabled or disabled by the ur; when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a ries of three program commands to specific address with specific data must be performed. After the software data protection is enabled the same three program com-mands must begin each program cycle in order for the programs to occur. All software program commands must obey the ctor program timing specifications. The SDP feature protects all ctors, not just a single ctor. Once t, the software data protection feature remains active unless its disable command is issued. Power transitions will not ret the software data protec-tion feature, however the software feature will guard against inadvertent program cycles during power transitions.
After tting SDP, any attempt to write to the device without the three-byte command quence will start the internal write timers. No data will be written to the device; however, for the duration of t WC , a read operation will effectively be a polling operation.
After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pul on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 256 bytes of data must be loaded into each ctor by the same procedure as outlined in the program ction under device operation.
4.5Hardware Data Protection
Hardware features protect against inadvertent programs to the AT29C040A in the following ways: (a) V CC n – if V CC is below 3.8V (typical), the program function is inhibited; (b) V CC power on delay – once V CC has reached the V CC n level, the device will automatically time out 5 ms (typical) before programming; (c) Program inhibit – holding any one of OE low, CE high or WE high inhibits program cycles; and (d) Noi filter – puls of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
4.6Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be accesd by hardware or software operation. The hardware operation mode can be ud by an external progr
h里番ammer to identify the correct programming algorithm for the Atmel product. In addition, urs may wish to u the software product identification mode to identify the part (i.e. using the device code), and have the system software u the appropriate ctor size for program operations. In this manner, the ur can have a common board design for 256K to 4-megabit densities and, with each density’s ctor size in a memory map, have the system soft-ware apply the appropriate ctor size.
For details, e Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.
4.7DATA Polling偏旁部首名称
The AT29C040A features DATA polling to indicate the end of a program cycle. During a pro-gram cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle.
4.8Toggle Bit
In addition to DATA polling the AT29C040A provides another method for determining the end of a program or era cycle. During a program or era operation, successive attempts to read
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data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.
4.9Optional Chip Era Mode
The entire device can be erad by using a 6-byte software code. Plea e Software Chip Era application note for details.
4.10Boot Block Programming Lockout
The AT29C040A has two designated memory blocks that have a programming lockout feature. This f
eature prevents programming of data in the designated block once the feature has been enabled. Each of the blocks consists of 16K bytes; the programming lockout feature can be t independently for either block. While the lockout feature does not have to be activated, it can be activated for either or both blocks.
The two 16K memory ctions are referred to as boot blocks . Secure code which will bring up a system can be contained in a boot block. The AT29C040A blocks are located in the first 16K bytes of memory and the last 16K bytes of memory. The boot block programming lockout feature can therefore support systems that boot from the lower address of memory or the higher address. Once the programming lockout feature has been activated, the data in that block can no longer be erad or programmed; data in other memory locations can still be changed through the regular programming methods. To activate the lockout feature, a ries of ven program commands to specific address with specific data must be performed. Plea e Boot Block Lockout Feature Enable Algorithm.
If the boot block lockout feature has been activated on either block, the chip era function will be disabled.
4.10.1
Boot Block Lockout Detection
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A software method is available to determine whether programming of either boot block ction is locked out. See Software Product Identification Entry and Exit ctions. When the device is in the software product identification mode, a read from location 00002H will show if programming the lower address boot block is locked out while reading location 7FFF2H will do so for the upper boot block. If the data is FE, the corresponding block can be programmed; if the data is FF, the program lockout feature has been activated and the corresponding block cannot be pro-grammed. The software product identification exit mode should be ud to return to standard operation.
5.Absolute Maximum Ratings*
T emperature -55°C to +125°C *NOTICE:
Stress beyond tho listed under “Absolute Maximum Ratings” may cau permanent dam-age to the device. This is a stress rating only and functional operation of the device at the or any other conditions beyond tho indicated in the operational ctions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Storage -65°C to +150°C All Input Voltages (including NC Pins)
with Respect -0.6V to +6.25V All Output Voltages
with Respect -0.6V to V CC + 0.6V Voltage on OE
with Respect -0.6V to +13.5V
