小学生安全手抄报HT1380/HT1381
Serial Timekeeper Chip
Block Diagram
Pin Assignment
1September 18,2000
Features
方言的英语·Operating voltage:2.0V~5.5V
·Maximum input rial clock:500kHz at V DD =2V,2MHz at V DD =5V
·Operating current:less than 400nA at 2V,less than 1.2m A at 5V ·
TTL compatible -V IH :2.0V~V DD +0.3V at V DD =5V -V IL :-0.3V~+0.8V at V DD =5V
·Two data transmission modes:single-byte,or burst mode
·
Serial I/O transmission
·All registers store BCD format ·
HT1380:8-pin DIP package HT1381:8-pin SOP package
General Description
The HT1380/HT1381is a rial timekeeper IC which provides conds,minutes,hours,day,date,mont
h and year information.The number of days in each month and leap years are auto-matically adjusted.The HT1380/HT1381is de-signed for low power consumption and can operate in two modes:one is the 12-hour mode with an AM/PM indicator,the other is the 24-hour mode.
The HT1380/HT1381has veral registers to store the corresponding information with 8-bit data format.A 32768Hz crystal is required to provide the correct timing.In order to minimize the pin number,the HT1380/HT1381u a -rial I/O transmission method to interface with a microprocessor.Only three wires are required:(1)REST,(2)SCLK and (3)I/O.Data can be de-livered 1byte at a time or in a burst of up to 8bytes.
Applications
·
Microcomputer rial clock ·Clock and Calendar
r r r
Pad Assignment Pad Coordinates Unit:m m
Pad No.X Y
1-851.40775.00
2-851.40494.60
3-844.40-203.90
4845.90-618.30
5848.40-4.30
6845.90332.60
7844.40572.60 Chip size:2010´1920(m m)2
*The IC substrate should be connected to VSS in the PCB layout artwork.
Pad Description
Pad No.Pad Name I/O Internal
Connection Description 1X1I CMOS32768Hz crystal input pad
2X2O CMOS Oscillator output pad
3VSS¾CMOS Negative power supply,ground
4REST I CMOS Ret pin with rial transmission
5I/O I/O CMOS Data input/output pin with rial transmission
6SCLK I CMOS Serial clock pul pin with rial transmission
7VDD¾CMOS Positive power supply
Absolute Maximum Ratings
.-0.3V to5.5V -50°C to125°C V SS-0.3V to V DD+0.3V 0°C to70°C Note:The are stress ratings only.Stress exceeding the range specified under²Absolute Maxi-mum Ratings²may cau substantial damage to the device.Functional operation of this de-vice at other conditions beyond tho listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
耳机接触不良
睡衣排行榜2September18,2000
D.C.Characteristics Ta=25°C
Symbol Parameter
Test Conditions
Min.Typ.Max.Unit V DD Conditions
V DD Operating Voltage¾¾2¾ 5.5V
I STB Standby Current 2V
¾
¾¾100nA 5V¾¾100nA
I DD Operating Current 2V
No load
¾0.7 1.0m A 5V¾0.7 1.2m A
I OH Source Current 2V V OH=1.8V-0.2-0.4¾mA 5V V OH=4.5V-0.5-1.0¾mA
I OL Sink Current 2V V OL=0.2V0.7 1.5¾mA 5V V OL=0.5V 2.0 4.0¾mA
V IH²H²Input Voltage5V¾2¾¾V V IL²L²Input Voltage5V¾¾¾0.8V f OSC System Frequency5V32768Hz X¢TAL¾32768¾Hz
f SCLK Serial Clock 2V
¾
¾¾0.5MHz 5V¾¾2MHz
*I STB is specified with SCLK,I/O,REST open.The clock halt bit must be t to logic1(oscillator disabled).
A.C.Characteristics Ta=25°C
Symbol Parameter
Test Conditions
Min.Max.Unit V DD Conditions
t DC Data to Clock Setup 2V¾200¾
ns 5V¾50¾
t CDH Clock to Data Hold 2V¾280¾
ns 5V¾70¾
t CDD Clock to Data Delay 2V¾¾800
南京香肚ns 5V¾¾200
t CL Clock Low Time 2V¾1000¾
ns 5V¾250¾
t CH Clock High Time 2V¾1000¾
ns 5V¾250¾
f CLK Clock Frequency 2V¾¾0.5
MHz
5V¾ D.C. 2.0
3September18,2000
Symbol Parameter蜡的拼音
Test Conditions
Min.Max.Unit V DD Conditions
t r
Clock Ri and Fall Time 2V¾¾2000
ns
t f5V¾¾500
t CC Ret to Clock Setup 2V¾4¾
us 5V¾1¾
t CCH Clock to Ret Hold 2V¾240¾
ns 5V¾60¾
t CWH Ret Inactive Time 2V¾4¾
us 5V¾1¾
t CDZ Ret to I/O High Impedance 2V¾¾280
ns
5V¾¾70
4September18,2000
Functional Description
街头象棋残局The HT1380/HT1381mainly contains the fol-lowing internal elements:a data shift register array to store the clock/calendar data,com-mand control logic,oscillator circuit and read timer clock.The clock is contained in eight read/write registers as shown below.Data con-tained in the clock register is in binary coded decimal format.
Two modes are available for transferring the data between the microprocessor and the HT1380/HT1381.One is in single-byte mode and the other is in multiple-byte mode.
The HT1380/HT1381also contains two addi-tional bits,the clock halt bit(CH)and the write protect bit(WP).The bits control the opera-tion of the oscillator and so data can be written to the register ar
ray.The two bits should first be specified in order to read from and write to the register array properly.
Command byte
For each data transfer,a Command Byte is initiated to specify which register is accesd.This is to determine whether a read,write,or test cycle is operated and whether a single byte or burst mode transfer is to occur.Refer to the table shown below and follow the steps to write the data to the chip. First give a Command Byte of HT1380/HT1381,and then write a data in the register.
This table illustrates the correlation between Command Byte and their bits:
Command Byte
Function Description C7C6C5C4C3C2C1C0 Select Read or Write Cycle R/W Specify the Register to be Accesd A2A1A0
Clock Halt Flag C
For IC Test Only1001x x x1 Select Single Byte or Burst Mode1011111x Note:²x²stands for don¢t care
The following table shows the register address and its data format:
Register Name Range
Data
Register Definition Address
A2~A0
Bit
R/W
Command
Byte D7D6D5D4D3D2D1D0
Seconds00~59CH10SEC SEC000W R10000000
10000001
Minutes00~59010MIN MIN001W R10000010
10000011
Hours01~12
00~2312\
24
AP
10
HR
HR HOUR010
W
R
10000100
10000101
Date01~310010DATE DATE011W R10000110
10000111
Month01~1200010M MONTH100W R10001000
10001001
Day01~070000DAY101W R10001010
10001011
Year00~9910YEAR YEAR110W R10001100
10001101
Write
Protect00~80WP ALWAYS ZERO111W
R
10001110
阴阳两虚怎么调理
10001111
CH: WP:Clock Halt bit
CH=0oscillator enabled
CH=1oscillator disabled
Write protect bit
WP=0register data can be written in WP=1register data can not be written in
Bit7of Reg2: Bit5of Reg2:12/24mode flag
bit7=1,12-hour mode bit7=0,24-hour mode AM/PM mode defined AP=1PM mode
AP=0AM mode
R/W signal
The LSB of the Command Byte determines whether the data in the register be read or be written to.
When it is t as²0²means that a write cycle is to take place otherwi this chip will be t into the read mode.
A0~A2
A0to A2of the Command Byte is ud to specify which registers are to be accesd.There are eight registers ud to control the month data, etc.,and each of the registers have to be t as
a write cycle in the initial time.
Burst mode
When the Command Byte is10111110(or 10111111),the HT1380/HT1381is configured in burst mode.In this mode the eight clock/calen-dar registers can be written(or read)in ries, starting with bit0of register address0(e the timing on the next page).
Test mode
When the Command Byte is t as1001xxx1, HT1380/HT1381is configured in test mode.
The test mode is ud by Holtek only for testing purpos.If ud generally,unpredictable con-ditions may occur.
5September18,2000
