AVR CPU Core
Introduction This ction discuss the AVR core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 3. Block Diagram of the AVR MCU Architecture
In order to maximize performance and parallelism, the AVR us a Harvard arc hitecture
– with parate memories and bus for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle. The program memory is In-
System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpo working registers with
a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File,
the operation is executed, and the result is stored back in the Register File – in one
clock cycle.
Six of the 32 registers can be ud as three 16-bit indirect address register pointers for
Data Space addressing – enabling efficient address calculations. One of the the
address pointers can also be ud as an address pointer for look up tables in Flash Program memory. The added function registers are the 16-bit X-, Y-, and Z-register,
described later in this ction.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
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32 x 8
General
Purpo
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressi ng
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n
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an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two ctions, the Boot program ction and the Application Program ction. Both ctions have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory ction must reside in the Boot Program ction.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and conquently the Stack size
is only limited by the total SRAM size and the usage of the SRAM. All ur programs must initialize the SP in the ret routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accesd through th e five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register. All interrupts have a parate interrupt vector in the interrupt vector table. The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority. The I/O memory space contains 64 address for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accesd directly, or as the Data Space locations following tho of the Register File, $20 - $5F.
ALU –Arithmetic Logic
Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpo workin
g registers. Within a single clock cycle, arithmetic operations between general purpo registers or between a register and an immediate are executed. The
ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier
supporting both signed/unsigned multiplication and fractional fo rmat. See the “Instruction Set” ction for a detailed description.
Status Register The Status Register contains information about the result of the most recently executed
arithmetic instruction. This information can be ud for altering program flow in or der to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cas
remove the need for using the dedicated compare instructions, resulting in fast er and
more compact code.
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The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.
The AVR Status Register – SREG – is defined as:
白琴Bit 7 6 5 4 3 2 1 0
I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be t for the interrupts to be enabled. The individual interrupt enable control is then performed in parate control registers. If the Global Interrupt Enable Register
is cleared, none of the interrupts are enabled independent of
the individual interrupt enable ttings. The I-bit is cleared by hardware after an interrupt
has occurred, and is t by the RETI instruction to enable subquent interrupts. The Ibit
can also be t and cleared by the application with the SEI and CLI instructions, as described in the instruction t reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) u the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied
into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
夸夸同学的闪光点The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is uful in BCD arithmetic. See the “Instruction Set Description” for detaile d information.
• Bit 4 – S: Sign Bit, S = N ⊕V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 –V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See
the “Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See
the “Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.
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General Purpo
Register File
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The Register File is optimized for the AVR Enhanced RISC instruction t. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:站在巨人的肩膀上
消防控制室• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 4 shows the structure of the 32 general purpo working registers in the CPU.
Figure 4. AVR CPU General Purpo Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.
As shown in Figure 4, each register is also assigned a data memory address, mapping
them directly into the first 32 locations of the ur Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great
flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be t to index any register in the file.
7 0 Addr.
R0 $00
R1 $01
R2 $02
…
R13 $0D
General R14 $0E
Purpo R15 $0F
Working R16 $10
Registers R17 $11
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R26 $1A X-register Low By te
R27 $1B X-register High Byte
R28 $1C Y-register Low By te
R29 $1D Y-register High By te
R30 $1E Z-register Low By te
R31 $1F Z-register High Byte
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The X-register, Y-register and
Z-register
The registers R26..R31 have some added functions to their general purpo usage.
The registers are 16-bit address pointers for indirect addressing of the Data Space.
The three indirect address registers X, Y, and Z are defined as described in Figure 5.
Figure 5. The X-, Y-, and Z-registers
In the different addressing modes the address registers have functions as fixed displacement,
automatic increment, and automatic decrement (e the Instruction Set
Reference for details).
Stack Pointer The Stack is mainly ud for storing temporary data, for storing local variables and for
storing return address after interrupts and subroutine calls. The Stack Pointer Regis ter always points to the top of the Stack. Note that the Stack is implemented as growing
from higher memory locations to lower memory locations. This implies that a Stack
PUSH command decreas the Stack Pointer. If software reads the Program Counter
from the Stack after a call or an interrupt, unud bits (15:13) should be masked out.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be t to point above $60. The Stack Pointer is decremented by one when
data is pushed onto the Stack with the PUSH instruction, and it is decremented by two
when the return address is pushed onto the Stack with subroutine call or interrupt. The
Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return
from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number
of bits actually ud is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this
ca, the SPH Register will not be prent.
15 XH XL 0
X - register 7 07 0
R27 ($1B) R26 ($1A)
