An Analytic Model for Heterojunction Tunnel FETs With Exponential Barrier

更新时间:2023-05-31 12:30:32 阅读: 评论:0

An Analytic Model for Heterojunction Tunnel FETs With Exponential Barrier
Yuan Taur,Fellow,IEEE,Jianzhi Wu,Student Member,IEEE,and Jie Min,Student Member,IEEE
Abstract—This paper prents an analytic model for double-gate tunnel FETs with an exponential barrier. By carrying out the Wentzel–Kramer–Brillouin integral in clod form,an I–V model is formulated in terms of a single integral of a continuous function with respect to energy.The model shows that source degeneracy helps the linear region I ds–V ds characteristics,but degrades the saturation current.Also inves-tigated is the role of the effective density of states on the debiasing of V gs due to channel inversion charge at low V ds.
A high effective density of states is shown to lead to superlinear I ds–V ds characteristics.
Index Terms—Band-to-band tunneling,heterojunction, tunnel FET(TFET).
I.I NTRODUCTION
R ECENTLY,there is a great deal of interest in tunnel FETs(TFETs)[1]–[5]becau of their promi to deliver steep turn-off slopes,hence enabling the reduction of supply voltage to below0.5V.An inherent prob-lem with TFETs is their low ON-currents.Staggered het-erojunctions have been propod to bo
ost the ON-current by lowering the barrier height for band-to-band tunneling at the source junction[2].Abrupt band offts at the heterojunction boundary,however,render the conven-tional uniformfield approximation for tunneling probability inapplicable.大智若愚反义词
In this paper,wefirst show that the tunneling barrier in a double-gate(DG)or nanowire(NW)TFET is of an exponential nature with a decay length related to the cross-ctionalfilm thickness or diameter.An analytic model is then derived by carrying out the Wentzel–Kramer–Brillouin(WKB) integral for the exponential barrier in clod form.I–V curves are generated for the1-D ca with a single integral of the tunneling probability as a continuous function of energy.The model is ud to investigate the effect of source degeneracy on the ON-current and turn-off slope, as well as the drain debiasing effect on linear region characteristics.
Manuscript received October19,2014;revid December2,2014and January17,2015;accepted February24,2015.Date of publication March10, 2015;date of current version April20,2015.The review of this paper was arranged by Editor R.Huang.
The authors are with the Department of Electrical and Computer Engineering,University of California at San Diego,La Jolla,CA92093USA (e-mail:ytaur@ucsd.edu).
Color versions of one or more of thefigures in this paper are available online at
Digital Object Identifier
六根清净什么意思
10.1109/TED.2015.2407695Fig.1.Schematic of DG TFET.
II.M ODELING OF2-D P OTENTIAL IN TFETs
2-D potential has been solved analytically for a conventional DG as well as NW MOSFETs in the abnce of mobile charge[6]–[9].The solution can be adopted by TFETs with a straightforward change of the source boundary condition from n+to p+.The assumption of negligible mobile charge is justified when the Fermi level is below the conduction band of the channel.The bias condition in w
hich mobile charge has a significant effect on the potential will be addresd later.Focusing on the mathematically simpler DG TFETs, we can express the analytic potential in the miconductor as a ries of eigenfunctions with discrete eigenvaluesλsatisfying
tan
πt i
λ
tan
πt s
=
εi
εs(1) where t i and t s are defined in Fig.1andεi andεs are the permittivities of the insulator and the s
emiconductor, respectively.To gain a physical insight into the meaning ofλ, consider the simple ca ofεi=εs,in which the solutions to(1)areλn=t s+2t i,(t s+2t i)/3,(t s+2t i)/5,...etc. The longestλ=t s+2t i is called the scale length,which is simply the vertical distance between the two gates.It should be pointed out that there is a different kind of scale lengths in the literature:tho derived from the“polynomial potential”models[10]–[12].They take some general form in terms of (t s t i)1/2.The polynomial potential-bad models have been discredited for not satisfying the2-D Poisson’s equation in the entire miconductor region,and for neglecting the lateralfield in the insulator[13].The scale lengths of the(t s t i)1/2type led to the incorrect asymptotic behavior in the limits of either t s t i or t s t i.Note that with the correct scale length,
0018-9383©2015IEEE.Personal u is permitted,but republication/redistribution requires IEEE permission.
See /publications_standards/publications/rights/index.html for more information.
Fig.2.(a)Conduction band energy at the center offilm for an example of t s=5nm and t i=2nm withεi=εs.The conduction band of the source is above the scale due to the band offt of heterojunction.(b)Approximation of the center and surface potential near the source with a single exponential function.The scale length isλ=9nm in this example.
λ=t s+2t i,λcannot be smaller than t s or2t i,whichever is larger.
The full2-D potential is the sum of the long-channel term,V gs− φ,and a ries of eigenfunctions with the x dependence
b n sinh[π(L−x)/λn]+
c n sinh[πx/λn]
sinh[πL/λn]
(2)
stemming from the source and drain boundary conditions[8]. Here,L is the channel length and φis the gate work function.b n and c n are the constants expresd in terms of the boundary conditions and thefilm thickness. Fig.2(a)shows an example of the solutions for two V gs values.The analytic solutions,consisting of four terms of the eigenfunctions(λ1,λ3,λ5,andλ7),are validated by the Sentaurus simulation[14].Note that a higher V gs caus a thinner barrier as well as a wider tunneling window from the source to the channel.
For TFETs biad in saturation,the current is mainly determined by the tunneling barrier near the source. In Fig.2(b),we zero in on the potential solution clo to the source,where the eigenfunctions are dominated by
the Fig.3.Band diagram of a heterojunction TFET biad in saturation. term∝sinh[π(L−x)/λ]/sinh[πL/λ]≈exp(−πx/λ). Depending on thefilm thickness,the potential has a slight variation between the surface and the center of the miconductor.To enable an analytic model for TFET, we approximate both the center and the surface poten-tials with a single exponential function,exp(−πx/λ)−1, whereλ=t s+2t i is the scale length[3]–[5].The
approximation of uniform potential in the depth direction is more valid for the ca of relatively thin t s and thick t i.
A similar function works for NW TFET as well,with λ=π(r s+t i)/αfor the caεi=εs,where r s is the NW radius andα=2.405is thefirst zero of the zeroth-order Besl function[9].
III.TFET M ODEL W ITH E XPONENTIAL B ARRIER The band diagram of a staggered heterojunction TFET is shown in Fig.  3.The zero energy reference is chon to be the conduction band energy of the channel at the heterojunction boundary.It staggers below the conduction band energy of the source by the band offt.The diagram is for the TFET biad in turn-ON and in saturation. Using the single exponent approximation,the potential bar-rier for electrons tunneling from the valence band of the source to the conduction band of the channel takes the form
V(x)=V0exp(−πx/λ)−V0(3) where V0is mainly controlled by the gate voltage.
For electrons at energy−E in the valence band, the tunneling probability as given by the WKB integral is
T(E)=exp
−2
2m
¯h
d
V(x)+Edx
=exp
−2
2m
¯h
d
V0e−πx/λ−V0+Edx
(4)
where V(d)+E=0.The integral can be carried out analytically to yield
T(E)=exp
−4λ
2m
π¯h
E−
V0−E sin−1
E/V0
.
蒸肉丸子(5)
TAUR et al.:ANALYTIC MODEL FOR HETEROJUNCTION TFETs
1401 Fig.4.Tunneling probability versus carrier energy.The tunneling window
is constrained by the density of states to E0<E<V0.
For a1-D ballistic TFET,the current is given by the Landauer
equation
I ds=2q
h
V
E0
(f s−f d)T(E)d E
=2q
h  V
E0
1
1+e(E1−E)/kT
−1
1+e(E2−E)/kT
×exp
−4λ
2m
π¯h
东北小克简介E−
V0−E sin−1
E/V0
d E
(6)
where E0,E1,and E2are the positive quantities defined in Fig.  3.Note that V ds=(E2−E1)/q.V gs is d
efined such that V gs=0corresponds to V0=,where the tunneling window starts to open up.This definition has the merit that the off condition is maintained at the same V gs for different designs,but it implies a choice of gate work function dependent on the band offt(E0)and source degeneracy(E1). For energies where f s−f d≈1,the current is proportional to the area under T(E)from E0to V0.Fig.4considers an example of m=0.1m0,λ=9nm(t s=5nm,t i=2nm, andεi=εs),and E0=0.15eV for veral values of V0(=qV gs+E0).It is clear that as V0or V gs increas, most of the current(area)gain comes from thinning of the barrier,rather than from expanding the tunneling window. It is also clear that a smaller E0resulting from a larger band offt would significantly rai the tunneling current. Too low an E0(<0.1eV)or broken gap(E0<0)designs, however,have been reported to result in subthreshold current swing>60mV/decade[15].
IV.M ODEL G ENERATED I–V C HARACTERISTICS
For a given material and doping,the band offt E0and source degeneracy E1arefixed.Continuous I ds(V gs,V ds) characteristics can be generated from(6)once the para-meters V and E2are expresd as continuous functions of V gs and V ds.It is straightforward that E2=E1+qV ds. For V,wefirst consider saturation in which the drain
Fermi Fig.5.(a)I ds versus V gs for source degeneracies,d1=E1−E0=0,0.05, and0.1eV(top to bottom).(b)Sentaurus simulation,in which the source degeneracy is varied by adjusting the valence band effective density of states with no change in the source doping.
慈吉中学
level is below the conduction band of ,E2>V0 in Fig.3,and V0is controlled only by V gs.With our choice of reference,V0=E0+qV gs.
In Fig.5(a),we plot I ds–V gs characteristics for veral values of the source degeneracy,d1=E1−E0.d1is adjusted independent of source doping,which is assumed to be high enough that there is no depletion in the source.By our definition,I ds=0at V gs=0,where V0=E0.In reality,there is a currentfloor t by the source-to-drain tunneling or by minority carrier generation and recombination not considered here.The heterojunction TFET example in Fig.5(a)is that of an AlGaAsSb source and InGaAs channel with E0=0.23eV. It is well known that the TFET turn-off slope is degraded by source degeneracy becau of the kT tail of the Fermi–Dirac distribution below the valence band edge.Here,we also obrve that the ON-current is degraded by higher source degeneracy.The underlying reason can be obrved in Fig.3. For a given E0,electrons at the top of the valence band e the lowest barrier.Source degeneracy pushes the electron population below the valence band edge,hence increas their barrier height for tunneling.Such effect is verified qualitatively by the Sentaurus simulations shown in Fig.5(b)[14].Too low a source doping of cour leads to reducedfield at the junction,
1402IEEE TRANSACTIONS ON ELECTRON DEVICES,VOL.62,NO.5,MAY 2015
longer tunneling path,and decread TFET current.There is an optimum source doping level in the range of mid-1019cm −3.A maximum TFET current can be derived from the analytic model in the limit of E 0=0(zero effective bandgap)and f s −f d =1.For E /V 0 1,(5)is approximated as
T (E )≈exp  −
4λ√2m π¯h E
3/23V 0 .(7)Equation (6)then gives
I =2q h
V 00exp  −8λ√2m 3hV 0
E
3/2
d E ≈2q h
3hV 08λ√2m  2/3 ∞0exp (−y 3/2)dy .
(8)
The numerical integral ≈0.9and V 0=qV gs .Therefore
I max =0.9q
3qV gs 4λ√
mh
2/3
.
(9)
For m =0.1m 0,λ=9nm,V gs =0.5V ,and I max ≈13μA.When the TFET is biad in the linear region,E 2approaches E 1and f d =0.Moreover,since the Fermi level in the channel is near or above the conduction band edge,there is a debiasing effect on V 0due to the channel inversion charge [3],[5].Instead of V 0=E 0+qV gs as in the high V ds ca,V 0is reduced to E 0+q (V gs −Q inv /C ox ),where Q inv /C ox is the potential drop across the gate insulator.This is an electrostatic effect unrelated to the transport.For a given V gs −V ds ,Q inv /C ox can be calculated from a continuous analytic solution of Poisson’s equation with mobile charge for DG MOSFETs [16]
Q inv =
4kT εs
qt s
βtan β(10)
where the intermediary parameter βis solved from an implicit equation
q (V gs −V ds −d 1)2kT −ln芸豆的做法
2t s
2εs kT
q 2N c
=ln β−ln [cos β]+
2εs t i
εi t s
βtan β.(11)
Here,N c is the effective density of states of the conduction band and d 1is the source degeneracy.They play a key role on the ont of debiasing versus V ds ,and therefore on the linear region characteristics.Fig.6shows three debiasing curves,one for silicon-like and two for InGaAs with different source degeneracies.The silicon-like ca assumes the N c of silicon,with everything el the same as the AlGaAsSb/InGaAs het-erojunction example considered in Fig.5.Table I summarizes the device parameters.The high N c of silicon results in a sig-nificant debias as soon as V ds is belo
w V gs +0.1V .The debias for InGaAs does not start until V ds is below V gs −0.05V if no source degeneracy,and below V gs −0.15V if there is a source degeneracy of 0.1eV .
To incorporate the debias effect in the generation of con-tinuous I ds (V gs ,V ds )characteristics from (6),we take an extra step to first calculate Q inv from (10)and (11)
for
Fig.6.Reduction of V 0in the linear region by Q inv in the channel.N c =3×1019cm −3for Si-like,N c =8.7×1016cm −3for InGaAs.εs =εi =14.6ε0for all cas.
TABLE I
D EVIC
E P ARAMETERS FOR THE E XAMPLES IN
F IGS .6AND 7
given V gs and V ds .Then,V 0is t to E 0+q (V gs −Q inv /C ox )in the current integral.At a fixed V g
s ,when V ds becomes high enough,V gs –V ds in Fig.6goes negative and Q inv →0.The corresponding I ds makes a smooth transition to the saturation value for that V gs .Fig.7(a)shows the model generated I ds –V ds characteristics for InGaAs,d 1=0.1eV with and without debias.In the no debias ca,the only V ds -dependent factor in (6)is f d .I ds saturates quickly when E fd is ∼0.15eV below E fs and the current becomes source injection limited.The effect of debias is to reduce the linear region current and push V dsat higher with no impact on I dsat .For the ca of InGaAs with d 1=0in Fig.7(b),the debias effect is more pronounced,resulting in higher V dsat .However,the magnitude of I dsat is significantly higher than that of d 1=0.1eV ,for reasons given earlier with Fig.5.The most vere debias happens with the silicon-like TFET in Fig.7(c).The high N c of silicon gives ri to the superlinear I ds –V ds characteristics.The trends are all confirmed qualitatively by Sentaurus simulations,as well as by published hardware data in [17]–[20].
The I ds –V ds characteristics in Fig.7are generated by (6)of the model with a modification that the low end of the tunneling window is limited by the E c of the channel or the E c of the drain,whichever is higher.In other words,the upper bound of the integral in (6)is given by V 0or E 0+V ds +d 1+d 2,whichever is lower.Here,d 2is the drain degeneracy.In practice,this makes only a very slight difference in I ds at V ds below 0.1V ,becau in that energy range,
TAUR et al.:ANALYTIC MODEL FOR HETEROJUNCTION TFETs
1403
Fig.7.Model generated I ds –V ds characteristics for the three debiasing conditions in Fig.6.The dashed curves in (a)are for no debiasing.
the tunneling path is long and both f s and f d ≈  1.There is a very little contribution to the tunneling current.V.C ONCLUSION
In conclusion,an analytic model is formulated for a DG TFET with an exponential potential barrier.The model
generates continuous I ds –V gs and I ds –V ds characteristics with a single integral over the tunneli
ng window.It provides insights into the effect of source degeneracy on linear and saturation region currents.It also shows that the debiasing of V gs by the channel inversion charge plays a key role in the saturation voltage and linearity of I ds –V ds curves.
A CKNOWLEDGMENT
Y .Taur would like to thank Dr.D.Frank and Dr.P.Solomon of International Business Machines Rearch for their inspiring discussions.The authors would also like to thank J.Ji of Peking University for his contribution to literature arch.
R EFERENCES
[1]  A.  C.Seabaugh and Q.Zhang,“Low-voltage tunnel transistors for
beyond CMOS logic,”Proc.IEEE ,vol.98,no.12,pp.2095–2110,Dec.2010.
[2]L.Wang,E.Yu,Y .Taur,and P.Asbeck,“Design of tunneling field-effect transistors bad on staggered heterojunctions for ultralow-power applications,”IEEE Electron Device Lett.,vol.31,no.5,pp.431–433,May 2010.
[3]P.M.Solomon,D.J.Frank,and S.O.Koswatta,“Compact model
巴黎十一大
and performance estimation for tunneling nanowire FET,”in Proc.69th Annu.Device Res.Conf.(DRC),Jun.2011,pp.197–198.
[4]L.Liu,D.Mohata,and S.Datta,“Scaling length theory of double-gate
interband tunnel field-effect transistors,”IEEE Trans.Electron Devices ,vol.59,no.4,pp.902–908,Apr.2012.
[5]  B.Rajamohanan,D.Mohata,A.Ali,and S.Datta,“Insight into the
output characteristics of III–V tunneling field effect transistors,”Appl.Phys.Lett.,vol.102,no.9,p.092105,2013.
[6]  D.J.Frank,Y .Taur,and H.-S.P.Wong,“Generalized scale length
for two-dimensional effects in MOSFETs,”IEEE Electron Device Lett.,vol.19,no.10,pp.385–387,Oct.1998.
[7]S.-H.Oh,D.Monroe,and J.M.Hergenrother,“Analytic description
of short-channel effects in fully-depleted double-gate and cylindrical,surrounding-gate MOSFETs,”IEEE Electron Device Lett.,vol.21,no.9,pp.445–447,Sep.2000.
[8]X.Liang and Y .Taur,“A 2-D analytical solution for SCEs in
DG MOSFETs,”IEEE Trans.Electron Devices ,vol.51,no.9,pp.1385–1391,Sep.2004.
[9]  B.Yu,L.Wang,Y .Yuan,P.M.Asbeck,and Y .Taur,“Scaling of
nanowire transistors,”IEEE Trans.Electron Devices ,vol.55,no.11,pp.2846–2858,Nov.2008.
[10]R.-H.Yan,A.Ourmazd,and K.F.Lee,“Scaling the Si MOSFET:From
bulk to SOI to bulk,”IEEE Trans.Electron Devices ,vol.39,no.7,pp.1704–1710,Jul.1992.
[11]K.Suzuki,T.Tanaka,Y .Tosaka,H.Horie,and Y .Arimoto,“Scaling
theory for double-gate SOI MOSFET’s,”IEEE Trans.Electron Devices ,vol.40,no.12,pp.2326–2329,Dec.1993.
[12]  C.P.Auth and J.D.Plummer,“Scaling theory for cylindrical,fully-depleted,surrounding-gate MOSF
ET’s,”IEEE Electron Device Lett.,vol.18,no.2,pp.74–76,Feb.1997.
[13]Q.Xie,J.Xu,and Y .Taur,“Review and critique of analytic models of
MOSFET short-channel effects in subthreshold,”IEEE Trans.Electron Devices ,vol.59,no.6,pp.1569–1579,Jun.2012.
[14]TCAD Sentaurus Device Manual ,Synopsys,Inc.,Mountain View,CA,
USA,2010.
[15]J.Knoch and J.Appenzeller,“Modeling of high-performance p-type
III–V heterojunction tunnel FETs,”IEEE Electron Device Lett.,vol.31,no.4,pp.305–307,Apr.2010.
[16]Y .Taur,X.Liang,W.Wang,and H.Lu,“A continuous,analytic drain-current model for DG MOSFETs,”IEEE Electron Device Lett.,vol.25,no.2,pp.107–109,Feb.2004.
[17]O.M.Nayfeh,J.L.Hoyt,and D.A.Antoniadis,“Strained-Si 1−x Ge x /Si
band-to-band tunneling transistors:Impact of tunnel-junction germanium composition and doping con
centration on switching behavior,”IEEE Trans.Electron Devices ,vol.56,no.10,pp.2264–2269,Oct.2009.[18]  A.Vandooren et al.,“Analysis of trap-assisted tunneling in vertical
Si homo-junction and SiGe hetero-junction tunnel-FETs,”Solid-State Electron.,vol.83,pp.50–55,May 2013.
>昂首高吭

本文发布于:2023-05-31 12:30:32,感谢您对本站的认可!

本文链接:https://www.wtabcd.cn/fanwen/fan/82/820208.html

版权声明:本站内容均来自互联网,仅供演示用,请勿用于商业和其他非法用途。如果侵犯了您的权益请与我们联系,我们将在24小时内删除。

标签:简介   芸豆   东北   做法
相关文章
留言与评论(共有 0 条评论)
   
验证码:
推荐文章
排行榜
Copyright ©2019-2022 Comsenz Inc.Powered by © 专利检索| 网站地图