External DCR Bus Interface I/O Signal Summary
Virtex-II Pro DCR Interface
Figure 2-32 shows the block symbol for the DCR interface. The signals are summarized in Table 2-21.
Virtex-4FX DCR Interface
The external general purpo Virtex-4FX DCR interface is identical to its predecessors with the following exceptions:•Dedicated, re-synchronization registers implemented in the PowerPC block.•
Interface signals are renamed
The re-synchronization registers allow decoupling of the internal PowerPC clock
frequency from the DCR bus transactions by re-synchronizing the interface to a dedicated DCR clock (CPMDCRCLK, e “Clock and Power Management Interface”). This ensures that the internal PowerPC clock frequency can be kept high regardless of DCR transaction speed.
The Table 2-22 describes the name mapping between the Virtex-4FX DCR interface signals relative to Virtex-II Pro signals.
Figure 2-32:
Virtex-II Pro DCR Interface Block Symbol
Table 2-21:
Virtex-II Pro DCR Interface I/O Signals Signal
I/O Type If Unud Function
C405DCRREAD O No Connect Indicates a DCR read request occurred.C405DCRWRITE O No Con
高空跳水nect Indicates a DCR write request occurred.C405DCRABUS[0:9]O No Connect Specifies the address of the DCR access request. C405DCRDBUSOUT[0:31]
O
No Connect or attach to input bus
The 32-bit DCR write-data bus.
DCRC405ACK
I 0Indicates a DCR access has been completed by a peripheral.
DCRC405DBUSIN[0:31]
I
0x0000_0000or attach to output bus
The 32-bit DCR read-data bus.
External DCR Bus Interface
Table 2-22:Virtex-4FX DCR Interface Name Correlation with Virtex-II Pro Names
Virtex-4FX Name Virtex-II Pro Names EXTDCRREAD C405DCRREAD
EXTDCRWRITE C405DCRWRITE
EXTDCRABUS[0:9]C405DCRABUS[0:9] EXTDCRDBUSOUT[0:31]C405DCRDBUSOUT[0:31] EXTDCRACK DCRC405ACK EXTDCRDBUSIN[0:31]DCRC405DBUSIN[0:31]
自信的好处
External Interrupt Controller Interface
DCR Interface 1:2 Clocking, Latched Acknowledge
The example in Figure2-36 assumes the following:
•The PowerPC405 DCR interface is clocked at half the frequency of the peripheral
containing the addresd DCR.
•The acknowledge signal is latched and forwarded with the DCR bus as shown in
男女野战视频
Figure2-31, page105.
•After the acknowledge signal is asrted, it is not deasrted until the appropriate
成语接龙游戏规则read-access or write-access request signal is deasrted.
Note:Abbreviated signal names are ud.
Figure 2-36:DCR Interface 1:2 Clocking, Latched Acknowledge
External DCR Timing Consideration (Virtex-II Pro)
Urs need to be aware that there is no DCR clock input to the processor block of the
Virtex-II Pro FPGAs. When dealing with signals that cross CPU clock domain and DCR
clock domain, urs may want to add re-synchronization flip-flops to simply timing
constraints, or t up appropriate multi-cycle/fal path constraints in the UCF file.
An example for the re-synchronization of DCR interface can be found in Xilinx Embedded
Development Kit (EDK). Plea refer to the Virtex-II Pro PowerPC405 wrapper IP
datasheet (DS304) for details.
The Virtex-4FX family does have a DCR clock input and does not have the
synchronization issues mentioned here.
External Interrupt Controller Interface
The PowerPC embedded-environment architecture defines two class of interrupts:
critical and noncritical. The interrupt handler for an external critical interrupt is located at
exception-vector offt 0x0100. The interrupt handler for an external noncritical interrupt
is located at exception-vector offt 0x0200. Generally, the processor prioritizes critical
interrupts ahead of noncritical interrupts when they occur simultaneously (certain debug
exceptions are handled at a lower priority). Critical interrupts u a different save/restore
register pair (SRR2 and SRR3) than is ud by noncritical interrupts (SRR0 and SRR1). This
Chapter 2:Input/Output Interfaces
香蕉松饼的做法
Figure 2-37:
EIC Interface Block Symbol
Table 2-23:
EIC Interface I/O Signals
九尾狐妖朝鲜王朝Signal
I/O Type If Unud
威士忌品牌
Function
EICC405CRITINPUTIRQ I 0Indicates an external critical
interrupt occurred.
EICC405EXTINPUTIRQ
I
Indicates an external noncritical interrupt occurred.
PPC405 JTAG Debug Port
