Chapter 3:Core Architecture
Memory Settings
This ction captures the ttings of memory components and DIMMs.
有一种幸福叫珍惜DDR3 Register Module
DDR3 register module ttings are captured in Table 3-19. The register contents are programmed to default value of 0s, unless otherwi specified in the table. DDR4 Register Module
DDR4 register module ttings are captured in Table 3-20. The register contents are programmed to default value of 0s, unless otherwi specified in the table. Table 3-19:
DDR3 Register Module Settings Register
Field Possible Values and Description RC3
手机网游DBA[1:0], DA[4:3]Value bad on DRAM loads on the card.RC4
DBA[1:0], DA[4:3]Value bad on DRAM loads on the card.RC5
史敬思
DBA[1:0], DA[4:3]Value bad on DRAM loads on the card.RC10DBA[0], DA[4:3]Value bad on the targeted speed.RC11DA[4:3]
Value bad on the targeted voltage.Table 3-20:
高热量食物一览表
DDR4 Register Module Settings Register
怕冷的人Field Possible Values and Description RC03
DA[3:0]Value bad on DRAM loads on the card.RC04
DA[3:0]Value bad on DRAM loads on the card.RC05DA[3:0]Value bad on DRAM loads on the card.
RC08DA[1:0]
For non-3DS configurations:
01 = Number of physical ranks per slot is 4 (LRDIMM Quad rank)
旧金山景点11 = Number of physical ranks per slot is 2 or 1
For 3DS configurations:11 = 1 height
10 = 2 height
01 = 4 height
DA[3]0 = If address pins are 18
1 = If address pins are 17
四川事件RC0A DA[2:0]Value bad on the targeted speed.
RC0B DA[3]
1 = Input receiver Vref source is External VrefCA input
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