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Abstract- Modern System-on-Chip (SoC) environments are swamped in high frequency noi that is generated by RF and digital circuits and propagated onto supply rails through capacitive coupling. In the systems, linear regulators are ud to shield noi-nsitive analog blocks from high frequency fluctuations in the power supply. This work prents a low dropout regulator that achieves Power Supply Rejection (PSR) better than -40dB over the entire frequency spectrum. The system has an output voltage of 1.0V and a maximum current capability of 10mA. It consists of operational amplifiers (op amps), a bandgap reference, a clock generator, and a charge pump and has been designed and simulated using BSIM3 models of a 0.5µm CMOS process obtained from MOSIS.
I. I NTRODUCTION
The 21st century has witnesd an explosion in the demand for portable applications, such as cellular phones and personal digital assistants (PDAs) [1]. The principal requirements for the applications are low cost, high integration, and small size [2]. The requirements are pushing the design of SoC solutions, where den analog and digital circuits are fabricated on the same die [3]. The SoC environments are plagued by noi, generated by the switching of digital circuits, RF blocks, and dc-dc converters, that can have amplitudes of the order of hundreds of millivolts and frequency components in the range of tens of kilohertz to hundreds of megahertz [4]-[7]. This noi, propagated onto the supplies through crosstalk, deteriorates the performance of nsitive analog blocks, like the synthesizer and VCO, and manifests itlf as jitter in their output [4], [5], [8]-[11]. This jitter, in turn, deleteriously impacts critical system specifications like the lectivity of the receiver, spectral purity of the transmitter, and pha error tolerance of digital circuits [4]. In such an environment, a linear regulator is entrusted with the task of shielding noi-nsitive blocks from high frequency fluctuations in the power supply [3]-[5], [9]-[15]. This makes the design of linear regulators that have a high PSR over a wide frequency range extremely critical for high system performance.
Another important requirement for regulators for SoC applications is low dropout [4]. As supply volta
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ges for portable applications continue to shrink, maintaining PSR performance while reducing a regulator’s dropout voltage, the minimum voltage difference between its supply and output for accurate operation, is critical. Further, as systems aggressively
V. Gupta is with the Georgia Tech Analog and Power IC Design Lab, Georgia Institute of Technology, Atlanta, GA 30318 USA (email: vishalg@ece.gatech.edu, phone: 404 894 1299).
G. A. Rincón-Mora is with the Georgia Tech Analog and Power IC Design Lab, Georgia Institute of Technology, Atlanta, GA 30318 USA (email: rincon-mora@ece.gatech.edu).
advance towards integration, the state-of-the-art regulators are increasingly integrated “on-chip” and deployed at the point-of-load, with output currents in the range of 10 – 50 mA [9]–[15]. This strategy allows the regulators to be optimized to cater to the specific demands of the sub-systems that load them [4]. Also, on-chip capacitors (10-200 pF) can often be ud for frequency compensation [9]-[15], thereby conrving board-space and leading to increasing levels of integration. Since the regulators do not u an external capacitor to establish the dominant low-frequency pole, they are termed “internally compensated regulators”.
In this work, the basic linear regulator and current schemes ud for obtaining high PSR performanc
e are discusd in Section II. Section III prents the system and circuit level description of the propod technique. Section IV prents the simulation results. Conclusions are drawn in Section V.
II. B ACKGROUND
A. Basic Linear Regulator
Fig. 1 depicts the block diagram of a typical internally compensated regulator consisting of an error amplifier, a pass device, and output capacitor C out , which establishes output pole p out [3]-[5], [9]-[15]. The amplifier is characterized by its transconductance, output resistance R o-A , and corresponding bandwidth BW A , which determines the dominant pole in internally compensated regulators. The effective capacitance at the output of the error amplifier C o-A can be produced through Miller compensation or a capacitor to ground for the ca of a PMOS or NMOS output stage, respectively. The large ries pass device (NMOS or PMOS) has a high transconductance and low drain-source ries resistance. Bias resistors R 1 and R 2 are the feedback network and are typically very large for low quiescent power consumption.
or NMOS).
B. Current Techniques to Obtain High PSR
The analysis of the PSR of linear regulators follows readily from that of operational amplifiers, which have been analyzed
A Low Dropout, CMOS Regulator with High
PSR over Wideband Frequencies
Vishal Gupta, Student Member, IEEE, and Gabriel A. Rincón-Mora, Member, IEEE梦幻元宵活动
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in [11], [16]-[18]. In [19], an intuitive, potential-divider-bad model for analyzing the PSR of linear regulators over a wide range of frequencies was prented. Curves ‘1’ and ‘2’ in Fig. 2 reprent a typical PSR curve of a conventional internally compensated linear regulator, without and with the prence of Equivalent Series Resistance (ESR) of C out [19]. The model predicted that the PSR at low frequencies, its dominant zero, and two subquent poles corresponded to the dc open loop gain (A ol β), the bandwidth of the error amplifier (BW A ), the unity-gain frequency of the system (U
顶管GF), and the output pole (p out ), respectively. The curves indicate the worst-ca PSR occurs in the vicinity of the UGF of the system, typically in the range of 1-10MHz [9], [10], [16]-[19]. Intuitively, the loop gain provides high supply ripple rejection at low frequencies, while the output capacitor shunts any ripple appearing at the output to ground at very high frequencies.
宝贝成长记录Fig. 2. PSR curve of a linear regulator.
Numerous techniques have been ud to improve the PSR of linear regulators. The simplest solution is to place an RC filter in line with the power supply to filter out fluctuations before they reach the regulator [5], as shown in Fig. 3(a). This adds a pole to the PSR curve at the filter’s corner frequency, as shown by curve ‘3’ in Fig. 2. However, for an integrated SoC solution, the high power loss and reduction in voltage headroom caud by this resistor would verely limit its size, pushing the pole to very high frequencies. Another methodology, shown in Fig. 3(b), employs two linear regulators in ries to effectively “double” the PSR [5]. This method has the obvious disadvantage of incread power dissipation and voltage headroom. Also, obtaining a high PSR over a wide frequency range is still prohibitive, given that both regulators have similar limitations.
Fig. 3(c) prents a methodology that utilizes an NMOS cascode for the NMOS pass device of the li
word转成图片near regulator, thereby isolating it from the noisy power supply [9]. The gate of the cascoding NMOS and the supply of the error amplifier have been boosted using two charge pumps in order to yield a low dropout voltage. The error amplifier, however, cannot be similarly cascoded since the gate of its NMOS cascode would require a boosted voltage of two gate-source drops above the output, leading to higher circuit complexity. Hence, it us an RC filter to suppress fluctuations in the power supply and the systematic fluctuations of the charge pump. Since the error amplifier consumes a significant current for high bandwidth, and the resistor in the RC filter is large for a low corner frequency, the voltage drop across the resistor caus a large droop in the output voltage of the charge pump. Hence, the charge pump has been regulated, thereby adding complexity, layout area, and power consumption.
Fig.3. Previously implemented topologies for high PSR.
In [10], a PSR of -40 dB over a wide frequency range is achieved using an NMOS device to cascode the PMOS pass device of a linear regulator, as shown in Fig. 3(d). Due to relatively high voltage headroom (3.3V) the gate of the NMOS cascode is biad through the supply using a simple RC filter. The high voltage headroom also allows the error amplifier, which is powered directly from the supply, to u cascodes and gain boosting to improve its PSR performance. This increas circuit co
mplexity, dropout voltage, and power consumption. This work prents a topology that achieves a comparable PSR while exhibiting a lower dropout voltage, crucial for low-voltage, portable applications. The topology, described in the next ction, is prented in Fig. 4.
III. S YSTEM DESCRIPTION
A. NMOS Cascode
NMOS device M CAS , shown in Fig. 4, decouples the entire linear regulator from fluctuations in the power supply through its cascoding effect (effective ries resistance), thereby increasing PSR over a wide range of frequencies, as shown by curve ‘4’ in Fig. 2. Since the regulator has a low dropout, M CAS cascodes the error amplifier of the linear regulator along with its pass device, thereby eliminating the need for gain boosting ud in [10]. Further, the design us only one charge pump, as oppod to two in [9], thereby conrving layout area and reducing added noi. The charge pump, described next, boosts the voltage at the gate of M CAS to yield low dropout performance.
V I
V
V
V DD
V DD
Fig. 4. Block diagram of system.
B. Charge Pump
Fig. 5. Schematic of charge pump.
The charge pump boosts the voltage at the gate of the NMOS cascode to an optimal voltage level above the supply, to produce low dropout. The circuit has been optimized, using parasitic capacitors
C par and diodes D par across the output switches and a very low current sink I sink at the output, to produce a voltage lower than 2V DD so that M CAS is operating in saturation [9]. A simplified schematic of the topology implemented is prented in Fig. 5 [20]. The clock generator is an inverter chain, similar to that in [9].
C. RC Filter
Curve ‘4’ in Fig. 2 is valid if the gate of the cascode M CAS is an ideal ground. However, M CAS simply acts as a voltage follower for signals at its gate. Hence, it is absolutely critical to shield its gate from noi in the power supply, as this would be transferred without attenuation to the linear regulator at its source, producing curve ‘1’ in Fig. 2. This function is performed by the RC filter.
Referring to Fig. 4, the RC filter, comprising of R F and C F , filters out high frequency fluctuations in the power supply to attenuate power supply noi reaching the gate of the NMOS cascode and hence to the regulator through path ‘a’. In other words, the RC filter adds a pole to the path ‘a’, affecting the PSR curve in a manner similar to that of an RC filter in ries with the supply. However, since this RC filter is placed in a path that does not carry any dc current, the resistor can be made as large as practically possible, to yield a pole extremely clo to dominant zero (BW A ) of the PSR cur
ve ‘1’ in Fig. 2. Hence, the effective PSR of the system, following curve ‘1’ at low frequencies and curve ‘4’ at high frequencies, is traced by curve ‘5’ in Fig. 2. In this topology, the corner frequency of the RC filter is 3KHz, which has been obtained using a 700K Ω resistor and 70pF capacitor.
The RC filter also suppress the systematic ripple generated by the charge pump. Since the charge pump is connected the gate of the NMOS cascode through this RC filter and is not supplying current to an active load, it does not exhibit any droop in output voltage and has not been regulated, leading to lower circuit complexity.
D. Bandgap Reference
A schematic of the CMOS bandgap reference is prented in Fig. 7 [21]. The op amp in this circuit provides a loop gain of 60dB. The PSR of the bandgap reference is important as fluctuations at the output of the reference at frequencies lower than the gain bandwidth of the regulator, when the loop gain is greater than unity, can appear at the output of the regulator. However, the PSR of the bandgap reference can be significantly enhanced by increasing the loop gain of the op amp and by placing a relatively large capacitor C out_BG at its output to shunt the output ripple to ground at high frequencies [22], [23]. However this increas startup time of the circuit.
E. Op Amps
Fig. 7. Schematic of op amp OP2 u in bandgap reference (shaded region
shows OP1 ud in low dropout regulator) [18].
The two op amps in the system are OP1 and OP2 ud in the low dropout regulator, in Fig. 4 and the bandgap reference, in Fig. 6. Their schematics are prented in Fig. 7. The PSR of OP2 has been improved by eliminating the feedforward path of the Miller capacitor by using the grounded gate cascode technique described in [18]. This topology produces a worst-ca PSR of 30 dB. However, it is difficult to implement this
成公
(b)
(d)
topology as a regulator with M OUT as the pass device since the condition that ensures stability for this circuit requires cascode devices M C1 and M C2 to have a higher transconductance than that output device M OUT , [18] which is difficult to satisfy if the latter has to source large dc currents. PSR performance at low frequencies can be improved by implementing this op amp as a buffer preceding the charge pump. Op amp OP1 is shown in the shaded region in Fig. 6.
IV. S IMULATION R ESULTS
This system was simulated using BSIM3 models of AMI’s 0.5µm CMOS process, obtained from MOSIS. The system was designed to source an output current of 10mA while maintaining an output voltage at 1.0V. Figs. 8(a) and 8(b) prent the output voltage as a function of temperature and load current for various supply voltages. The minimum voltage headroom required by the system is given by
{},V 2V ,V 4V max V sat ds out sat ds TP min DD −−−++= (1)
which, given a V TP of 0.9V for this process, is approximately
Fig. 8. (a) Temperature coefficient, (b) load regulation, (c) ripple at power supply, and (d) ripple at output of regulator, showing PSR of -40dB.
Figs. 8(c) and 8(d) show that a 10MHz, 200mVpp ripple at the power supply produces a 1mVpp ripple at V out . This simulation, at the lowest operating supply voltage of 1.6V and maximum load current of 10mA, shows that the worst-ca PSR of the system is -40dB. A PSR, comparable to that obtained in [9], [10] has been obtained by cascoding the error amplifier and pass device of a low dropout regulator from fluctuations in the power supply.
V. C ONCLUSIONS
A system that achieves a PSR better than -40d
B over a large bandwidth has been designed. The system has an output voltage of 1.0V and can source 10mA of current. It utilizes a simple NMOS cascoding device to shield a low dropout regulator from fluctuations in the power supply. The gate of the NMOS cascode has been boosted to voltages above the supply rail using a charge pump and has been kept free of high frequency supply fluctuations using a simple R
C filter and op amp. The system has been simulated in a 0.5µm CMOS process. In conclusion, a low-voltage scheme to obtain high PSR over a large bandwidth for a linear regulator for state-of-the-art SoC environments has been prented.
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