Noi Coupling Between Power/Ground Nets Due To Differential Vias Transitions in a Multilayer PCB描写花朵的词语
Abstract— Due to the increa in board density, routing traces on different layers becomes a widely ud strategy. Through-hole vias are often ud to connect the traces. Tho vias that penetrate power/ground plane pairs could cau noi coupling between signal and power/ground nets. At the same time, the need for clean signal transmitted to receivers results in a wide u of differential signals. This paper studies the noi coupling mechanism caud by a differential pair of vias penetrating power/ground plane pair using a physics-bad via-plane model combined with transmission line models for traces. A 26-layer printed circuit board with a pair of differential vias have been modeled. The simulated results clearly demonstrate the impact of ground vias and via stubs on noi coupling. Keywords—Differential signal, noi coupling between signal and power/ground nets, signal via transition, via capacitance, cavity model, ground vias, via stub
I.I NTRODUCTION
Signal vias are extensively ud to route signals from one layer to another due to the increasing component density on the printed circuit board surfaces. In addition to the simultaneous switching noi (SSN), signals transitioning through power/ground plane pair can also be a source of power bus noi [1-2].
The noi coupling from the signal to the power/ground nets can be explained by considering the current return path. Even if ground vias and decoupling capacitors are placed adjacent to the signal, a portion of current will return to its source by means of the displacement current between the power/ground planes.
Similarly, noi can also be coupled from power/ground nets to signal nets [7]. The noi from the power and ground planes may affect the integrity (quality) of the high-speed signal that propagates through the vias.
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This paper studies the noi coupling problems between the signal and power/ground nets due to differential via transition, using a physics-bad via-plane model combined with transmission line models for traces. Noi on power planes generates by signal via transitions as well as time- and frequency-domain effects on signal transmission due to power bus noi are shown in the following ctions.
II.M ODELING A PPROACH AND T EST G EOMETRY
The modeling approach ud in this paper is bad on the gmentation method [3]. The geometry under study is divided in transmission-line regions and a via-plane region. The regions are modele
d parately first, and then are connected by enforcing current and voltage continuities.
The specific test geometry is shown in Figure 1. It includes a 26-layer printed circuit board and two coupled signal vias transitioning a differential signal from the microstrip lines on the top surface of the PCB to striplines on inner layers. The printed circuit board has 12 solid planes for power supply and current return. The dimensions of the printed circuit board are 12″×10″, and the coupled microstrips and striplines with a 100Ohm differential impedance are both 200mils long. All the dielectric layers are assumed to have a dielectric constant of 4.4, and a loss tangent of 0.02. The signal vias are located at (6″, 4″) from the lower left corner of the board, spaced by 60mils center-to-center. The via radius is 11mils. Two ports (Ports 5 and 6 in Figure 1) between two inner planes are chon to reprent the ports in a power/ground plane pair. Ports 1 and 3 are located at the ends of the top microstrip traces, and port 2 and 4 at the ends of the striplines, as shown in Figure 1.
The multilayer PCB geometry is divided into multiple blocks at the middle of each solid plane. This approach is valid since a perfect TEM coaxial mode exists in the antipad regions. This means well-defined voltages and currents exist at every interface between the blocks. Figure 2 illustrates a typical block except the top and bottom ones that are microstrip structures. As clearly shown in Figure 2(a), the geometry of every block includes a pair of planes and multiple via portions that may
or may not be connected to the planes. The corresponding equivalent circuit model is shown in Figure 2(b), where a capacitor exists between a via portion and a
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Matteo Cocchini1, Jun Fan1, Bruce Archambeault2, James L. Knighten3, Xin Chang1, James L. Drewniak1,
Yaojiang Zhang1 and Samuel Connor2
1The UMR/MST EMC Laboratory, Missouri University of Science and Technology (former University of Missouri-
Rolla), Rolla, MO, USA
2IBM Corporation, RTP, NC, USA
3Teradata Corporation, San Diego, CA, USA
978-1-4244-1699-8/08/$25.00 ©2008 IEEE
plane if the via portion is not connected to the plane. The
plane pair is modeled as a multi- port impedance matrix, where a port is at every via portion. This via-plane model consisting of the cascading blocks is physics-bad [4, 6]. The equivalent circuit model for the entire test geometry was established using the previously introduced approach, and is shown in Figure 3. In this simplified model, the ground vias are not shown. There are eleven blocks in the model associated with the eleven plane pair. The via-plane capacitances are between the signals (direct path) and every plane. In this geometry under study, all the solid planes except plane 4 (a power plane) are considered to be ground planes. For the sake of simplicity, only the equivalent circuit for a through transition from the top microstrips to the bottom microstrips thru configuration) is shown in Figure 3.
Figure 1. Differential test geometry and stack-up to study noi coupling from
signal to power/ground nets.
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The capacitance values can be calculated using a quasi-static EM tool or a clod-form expression [4]. The plane pair is modeled as a multi-port impedance matrix that is obtained using the cavity method [5]. Loss in the metal planes and in the dielectric as well as reflections at the plane edges (assumed PMC), are included in the impedance matrix.
Port 1
Port 2
Port 3
Zpp
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Via 2
Via 1 Via 2 Via 3
Via 3 Via 1
Port 1
Port 2
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Port 3
III.T HE E FFECTS OF V IA S TUBS AND G ROUND V IAS Figure 4 shows the two configurations st
udied in this paper. Figure 4(a) shows the geometry where the two striplines (associated to Ports 2 and 4) are placed inside the eighth cavities, resulting in a relatively short via stubs. In Figure 4(b) the striplines are located in the fourth cavity with longer via stubs.
As en in Figure 1, two ground vias are placed 60 mils away from the signal via centers in some cas, so that the impact of the two ground vias can be studied as well.
Both the time- and frequency-domain simulations have been performed to show the impacts of various geometry variations on S-parameters and eye-diagrams.
Figure 4. Striplines connection for the (a) short, and (b) the long stub cas. Figures 5 and 6 show the simulated differential return and inrtion loss, respectively, where Ports 1 and 3 in Figure 4 forms the differential Port 1 and Ports 2 and 4 the differential Port 2.
The placement of the GND vias adjacent to the signal does not improve the results a lot, especially in the ca of long stubs. For the short stub ca, the GND vias are effective in the range between 12 and 20 GHz where the green curve is about 2dB lower than the black one in Figure 6.
without GND vias.
It is evident from Figure 6, that the long stub configurations prent a deep resonance at around 10GHz. This resonance prents a huge signal transmission loss in the nearby frequency range, and should be avoided for high-speed signals.
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Figure 6. Differential inrtion loss for short and long stub cas with and
without GND vias.
The reason for this big transmission loss appearing in the black and green curves is that the impedance looking into the stubs is clo to zero when frequency is clo to the resonant frequency. Adding GND vias can shift the resonance but cannot remove it. The GND vias could, at some cas, provide a lower-impedance return path for current and hence improving the inrtion loss at some frequencies.
The impact of stub length is shown in the time-domain as well in Figure 7, where eye diagrams for long and short stubs
are shown in Figure 7(a) and (b), respectively. The data signal has a pattern of a data rate of 20Gbit/s and a ri time of 10ps. As clearly shown, the eye pattern is completely clod for the long stub ca and widely open for the short stub ca. This dramatic difference is due to the fact that one dominant spectrum component of the signal (10 GHz) is clo to the stub resonant frequency shown in Figure 6.
Figure 7. Eye diagrams for a 20GBit/s data pattern for long (a) and short stub
(b) configuration without GND vias.
IV.N OISE C OUPLING FROM P OWER/G ROUND TO S IGNAL Noi coupling from power/ground nets to signal in both the frequency- and time-domains was then studied. A redefinition of the ports is necessary to convert the single-ended to the differential mode as illustrated in Figure 8. Since the interest has been focud on the effects of the power bus noi introduced by an IC switching at Port 3’ (100 mils from signal vias) or Port 4’ (5 inches away from signal vias), two ports, Port 1’ and Port 2’ are defined in a 100Ohm differential configuration. Again, for simplicity, in Figure 8 the model shown reprents a microstrips-to-microstrips through transition.
Figure 8. .Simplified equivalent circuit with differential ports.
The circuit model is first investigated in the frequency domain, and the modeled S-parameters among the redefined Ports 1’, 3’ and 4’ are shown in Figures 9 and 10, respectively. S
3
1
|
Figure 9. Transfer functions between Ports 1’ and 3’ in Figure 8 for short and
qq刷人气long stubs with and without GND vias.
The |S13|, which indicates the noi coupled from Port 3’ in the power bus to the top microstrip lines, is below -50dB up to
approximately 3 GHz. This amount of coupling is negligible. Above 3 GHz, the noi coupling could be as high as -20dB. As clearly shown in Figure 9, the noi coupling is stronger with the shorter stub is short below approximately 8 GHz. It is also noticeable that the prence of the GND vias does not
long stub with and without GND vias.
A similar behavior can be obrved in Figure 10 where the source of the power bus noi is located five more inches away from the signal vias. Obviously, due to the distance, the coupling is much smaller.
Figure 11 and 12 show the time-domain results. A ries of 1Amp triangular current puls with a fall/ri time of 0.2ns and a period of 2ns are applied to Port 3’ and Port 4’ to simulate the effect of switching noi on the signal. As clearly shown in the time-domain curves, for this particular tting of data-rate and ri time, a peak voltage noi of about 30 to
50mV is prent at the end of the microstrip traces when the noi source is clor. The maximum amplitude is for the ca with short stubs and without GND vias, which is consistent to the S-parameter curves. Similarly, moving the noi source farther away, the voltage noi is greatly reduc
ed as shown in V. N OISE C OUPLING FROM S IGNAL T O P OWER /G ROUND
Noi Coupling from signal to power/ground nets was also studied by applying a data signal at Port 1’ in Figure 8 and obrving noi at Port 3’ or Port 4’. Figure 13 shows the time-domain waveforms when Port 1’ is excited with a 5V signal
The data pattern is “010010001” in repetition. Port 2’ is terminated with a 100 Ω load impedance.
As clearly en in Figure 13, the voltage at Port 2’ has a magnitude clo to 5V, indicating the signal transmission loss is relatively small at the fundamental frequency. However, the
