Write-Back Technique for Single-Ended 7T SRAM cell Vazgen Melikyan, Aram Avetisyan, Davit Babayan, Karo Safaryan, Tigran Hakhverdyan
Synopsys Armenia CJSC, Arshakunyats 41, Yerevan, Armenia
Abstract - This paper prents the new Write-Back scheme, which solve the half-lect operation problem and faster than conventional Write-Back technique for memory array with ven-transistor (7T) single-ended static random access memory (SE-SRAM) bit cell. Data in the cells are nsitive and flipping can happen, so propod scheme improves the stability issue for half-lected cells without performance degradation.
Keywords – Memory; Static Random Access Memory; Write Back; stability; variation;
I. INTRODUCTION
Nowadays in portable SoCs (System-On-Chip) the low-power applications plays a big role, particularly targeted towards portable applications, such as wireless nsors, mobile phones, medical devices and etc., so they have to expend less energy, becau they run on battery. The significant amount of power
for this type of devices spent on memory access, which will reduce the battery life. To solve the issue, need to take a look on two main areas, keeping the supply voltage low and decrea the capacitance of word/bit lines. Moreover, the unstable read caud by disturbance from bit lines to data storage node weakens the read stability and limits the minimum supply voltage (V MIN).
Half-lect write becomes verer at a near-/subthreshold region due to larger threshold voltage (V th) variation at low supply voltage. Write-back (WB) schemes have been offered to eliminate the half-lect disturbance. The previous WB technique [1] requires full bit line discharging for read, which leads to performance degradation, the new fast WB scheme is exclusively developed for differential SRAM cells. Half-lect write becomes verer at a near-subthreshold region due to larger threshold voltage (V th) variation at low supply voltage. Write-back (WB) schemes have been propod to eliminate the half-lect disturbance. The WB technique requires full bit line discharging for read, which leads to performance degradation. The new WB scheme is exclusively developed for single-ended SRAM cells.
This paper demonstrates a 7T SRAM with improved cell stability to address the foregoing issues. The WB delay with the single-ended bit line architecture is accordingly boosted. The rest of the paper is organized as follows. In Section II, the schematic and operation of the conventional WB sch
emes are described. The propod WB scheme for single-ended bit line architecture are explained in detail in Section III and IV. In Section VII summarizes this paper.
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II. CONVENTIONAL Write-Back Techniques Unlected cells are significantly degraded by the write operation in neighboring cells. Conventional WB circuits are imposing penalty on half-lect issue elimination.
There are 2 types of WB schemes.
A.Previous solution
B.Fast local solution
A. Previous solution
For first solution data read from unlected columns and then write back is appropriate cell via D-latch, multiplexor feedback circuit, clearly shown in Fig. 1. Firstly, in lected cell the RWL is “1”, for write operation to start. At same time the data, which is loaded with data on WBL/WBL_N lines should go inside bit cell. After write operation the read operation stars, so the WB circuit first reading data from RBL and keep data in D-latch. However, with YS control signal the data will refresh in un
lected cell via Mux and write driver. The first disadvantage of this technique is that additional time is needed for reading data in write operation, as shown in Fig.
2. However, the WB scheme require long time for full RBL discharging.
B. Fast local solution
Write operation starts by enabling the write word line (WWL) of a lected row, so the appropriate local WBL[m] and WBLB[m] are loaded with data. However, local WBL[n] and WBLB[n] of the neighboring unlected cells are floating. Hence, unwanted current I disturb flows from WBL[n] and WBLB[n] to the cell storing data “0”, which acts like a write operation (Fig.4). The WB scheme first reading data from unlected cells and writing the read data into the WBL’s in the same columns. A fast WB operation is prented by leverage of a differential read and WB n amplifier. By inrting WB cells between local n amplifiers and local WBLs, the WB operation is executed within the LBL’s, which improves the WB delay. Fig. 3 explains the simplified bit line architecture with the fast WB technique. WB cycle starts by read condition. The inrted read operation quickly generates read data in the local RBL (local RBL[j]) due to the small capacitive load. The corresponding addressing signals /Row and /Column are activated to trigger the WB path and transf
er the data from local RBL[j] to local WBL[j] and local WBLB[j]. After this, a delayed WWL is enabled to write the read data into the half lected cells. This WB circuit is compod of four logic gates, as shown in the Fig. 3.h5新特性
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Fig. 1. Circuit implementation of the old WB technique. *Y. Morita et al.,
VLSI Symposium, 2007
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真假蜜蜡
Fig. 2. Timing diagram. *Y. Morita et al., VLSI Symposium, 2007
III. Propod Local Write-Back Technique for 7T SRAM Cell Half lected cells
One of the important aspects of SRAM design is data stability. There is a risk for data degradation during the write operation in unlected neighboring cells. This operation called half-lected write (Fig. 5). For instance, if write word line (WWL) is enabled, then write cycle will take place in a lected row. The corresponding local WBL is loaded with data. In that ca, in the neighboring unlected cells WBL is floating. Therefore, from the unlected WBL the unwanted current I disturb will flow to the cell, which is storing data “0”. This will be looks like a write operation. The picture is more unsafe in the super-threshold region, an SRAM cell. So the half-lected write decreas the cell stability and can flip the original data in unlected cells. To resolve the half-lected issue, write-back (WB) scheme should be ud. The main idea of WB scheme is that firstly needed to read the data from unlected cells and write the read data into the WBLs in the same columns, in other words to refresh the data. Hence, the old data will not be lost. Nevertheless, there are 2 WB schemes normal and fast. The normal WB schemes require long time for full RBL discharging, but can be ud for single ended SRAM cell. The fast WB scheme is faster than normal WB, but the SRAM cell should have differential read path, so it is not directly applicable to single-ended SRAM cells. The 2 schemes are prented in Fig. 6 and Fig. 7 respectively.
乘成语Fig. 3. Circuit implementation of the Fast Local solution.
Fig. 4. Simplified bit cell structure ud for Fast Local solution.
Fig. 5. Memory array structure for Half Selected cells.
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In the unlected column, a WB cycle starts by asrting the WB_enable condition. For that condition the responsible signals are addressing signals /X and /Y. If they are activated the inrted read operation quickly generates read data to trigger the WB path and transfer the data from Q to BL. After this, with the delay the WWL signal should be enabled to write the read data from unlected cell into itlf. The propod WB circuit is compod of tree transistors, as shown in the Fig. 6 and Fig. 7.
Fig. 6. Circuit implementation of the fast WB technique.
Fig. 7. Circuit implementation of the fast WB technique.
IV. OPERATIONS
A. Read Operation
Information read out from the propod SRAM bit cell is carried out via a single ended bit line (data-li
ne). Prior to the read operation, BL is pre-charged to and the read word line (RWL) is asrted high (W0 is high) to turn on the Mra, which is esntially applicable for reading “0”. For reading “1”, BL has to remains at pre-charged level (~VDD ) becau
transistor M6 is turned off. It is important to notice that only the read “0”, high to low transition is affected by the inrtion of the and that the read “1”, low to high transition will not be affected. As a result, reading “1” is directly nd from the pre-charged BL. In both the cas either reading “1” or “0”, storage nodes are isolated from the read current path. It results in reduced capacitive coupling noi due to BL and hence, significantly enhances the data stability during read and hold states. to turn on the write access transistor M5 that connects the pre-charged bit line (BL) to node Q. As both the inverters (INV1 and INV2) are strongly cross coupled, so forcing the node Q to “1” is difficult through a pass gate device (M5). Hence, weaken the pull down strength of INV2 by inrting a ries transistor, which is controlled by W0 to cut-off during write operation. In other words, is ud to weaken the strongly cross coupled inverters. Hence, it enhances the write-ability, even at lower operating voltages.
B. Write Operation
First of all, the bit line (BL), should be pre-charged then suppodly the values for Q and QB nets accordingly are “0” and “1”, at the same time the write word line (WWL) should be “1” to enable the M5 transistor, so in that ca the Q net and BL will be connected. Therefore, the information from BL will go into the cell, so to keep the value inside the cell, WWL should be disabled, by giving to the gate of M5 transistor “0”.
V. MEASUREMENT RESULTS
512-b SRAM with the propod technique has been designed in a 28-nm CMOS technology. Fig. 8 shows the architecture of the memory. The memory array is created with 16 physical rows and 32 physical columns, which are further divided into two banks. Each bank contains 16 columns, and one data output. The propod WB scheme is implemented for each bank Fig. 8. The peripheral circuits, such as n
amplifiers, control circuit are placed as shown in Fig.8.
Fig. 8.
Organization of the 512-b SRAM.
Fig. 9 shows the simulated waveforms of the propod and conventional WB operation. At VDD = 0.24 V, RWL is enabled 150 ns before the activation of WWL for reading the original data. After WWL is toggled, half lect is detected by the flipping of the output q[0] and qt[0] nodes. To measure the WB delay ud the interval between the two flipping of q[0] and qt[0].
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Fig. 9. Simulated WB waveforms at VDD = 0.24 V.
With a clock frequency of 100 KHz, the local WB operation (q[0] and qt[0]) takes 101.28ns, 15.6% less than the conventional WB delay of 120.14 ns (q[1] and qt[1]). In this ca the read data will be loaded into the local WBLs for the WB operation. Due to the fast read operation through the local RBLs, the additional delay for the inrted read operation is small enough to make the WB speed similar to read through the global bit lines.
VI. CONCLUSION
A 7T SRAM with W
B circuit technique for removing half-lect write is prented. The propod WB scheme for single-ended bit line scheme eliminates the data flipping opportunity and implement the half-lect-free write operation. The inrted read operation through the RWL facilitates the WB speed comparable with the normal read speed. The propod circuit techniques can be employed in SRAMs for UDVS systems where ultralow-voltage operation is strongly demanded. REFERENCES
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