Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Bad Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
8Mega x 16 Synchronous DRAM (SDRAM)
(Rev 1.6, 02/2007)
Features
• Fast access time from clock: 5/5.4 ns • Fast clock rate: 166/143 MHz • Fully synchronous operation • Internal pipelined architecture • 2M word x 16-bit x 4-bank • Programmable Mode registers - CAS# Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst stop function
• Auto Refresh and Self Refresh • 4096 refresh cycles/64ms • CKE power down mode • Single +3.3V power supply • Interface: LVTTL
• 54-pin 400 mil plastic TSOP II package • Lead-free package is available
Overview
The EM639165 SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write access to the SDRAM are burst oriented; access start at a lected location and continue for a programmed number of locations in a programmed quence. Access begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The EM639165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a lf-timed row precharge that is initiated at the end of the burst quence. The refresh functions, either Auto or Self Refresh are easy to u. By having a programmable mode register, the system can choo the most suitable modes to maximize its performance. The devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications.
Pin Assignment (Top View)
Key Specifications
EM639165
- 6/7
t CK3Clock Cycle time(min.) 6/7 ns t AC3Access time from CLK(max.) 5/5.4 ns t RAS Row Active time(min.) 42/42 ns t RC
Row Cycle time(min.)
60/63 ns
Ordering Information
Part Number Frequency Package EM639165TS-6G 166MHz TSOP II EM639165TS-6LG 166MHz TSOP II EM639165TS-7G 143MHz TSOP II EM639165TS-7LG缉毒警察作文
单眼近视
143MHz TSOP II
“L” indicates Low Power. “G” indicates Lead-free
Block Diagram
Pin Descriptions
Table 1. Pin Details of EM639165
Symbol Type Description
CLK Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
CKE Input
Clock Enable:CKE activates(HIGH) and deactivates(LOW) the CLK signal. If
CKE goes low synchronously with clock(t-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state of
output and burst address is frozen as long as the CKE remains low. When all
banks are in the idle state, deactivating the clock controls the entry to the Power
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Down and Self Refresh modes. CKE is synchronous except after the device
坚持用英语怎么说enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are
disabled during Power Down and Self Refresh modes, providing low standby
power.
BA0,BA1 Input
Bank Select: BA0,BA1 input lect the bank for operation.
Bank
BA1 BA0
Select
#A
BANK
0 0
#B
BANK
0 1
#C
BANK
1 0
#D
BANK
1 1
A0-A11 Input
Address Inputs: A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A8 with A10
defining Auto Precharge) to lect one location out of the 2M available in the
respective bank. During a Precharge command, A10 is sampled to determine if
all banks are to be precharged (A10 = HIGH). The address inputs also provide
the op-code during a Mode Register Set command.
CS# Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH.
CS# provides for external bank lection on systems with multiple banks. It is
considered part of the command code.
RAS# Input
Row Address Strobe:The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# and CS# are asrted "LOW" and CAS# is asrted
"HIGH," either the BankActivate command or the Precharge command is
lected by the WE# signal. When the WE# is asrted "HIGH," the
BankActivate command is lected and the bank designated by BS is turned on
to the active state. When the WE# is asrted "LOW," the Precharge command
is lected and the bank designated by BS is switched to the idle state after the
precharge operation.
CAS#Input Column Address Strobe:The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# is held "HIGH" and CS# is asrted "LOW," the column
access is started by asrting CAS# "LOW." Then, the Read or Write command
is lected by asrting WE# "LOW" or "HIGH."
WE# Input Write Enable: The WE# signal defines the operation commands in conjunction
with the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is ud to lect the BankActivate or Precharge command and Read or Write command.
LDQM, UDQM
Input
Data Input/Output Mask: Controls output buffers in read mode and masks Input data in write mode.
DQ0-DQ15 Input / Output Data I/O: The DQ0-15 input and output data are synchronized with the positive
edges of CLK. The I/Os are maskable during Reads and Writes. NC/RFU - No Connect: The pins should be left unconnected. V DDQ
Supply
DQ Power: Provide isolated power to DQs for improved noi immunity. ( 3.3V ± 0.3V )
V SSQ
Supply
DQ Ground: Provide isolated ground to DQs for improved noi immunity. ( 0 V )
V DD Supply Power Supply: +3.3V ± 0.3V V SS
Supply
Ground
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command State CKE n-1CKE n DQM BA 0,1A 10A 0-9,11 CS# RAS# CAS#WE#
BankActivate Idle (3) H X X V Row address L L H H
BankPrecharge Any H X X V L X L L H L PrechargeAll Any H X X X H X L L H L
年轻人的英语
Write
Active (3) H X X V L L H L L Write and AutoPrecharge Active (3) H X X V H Column
address (A0 ~ A8) L H L L Read
Active (3) H X X V L L H L H Read and Autoprecharge Active (3)
H X X V H
Column address (A0 ~ A8)
L H L H Mode Register Set Idle H X X OP code
L L L L
No-Operation Any H X X X X
X L H H H Burst Stop Active (4)
H X X X X
X L H H L Device Delect Any H X X X X X H X X X AutoRefresh Idle H H X X X X L L L H SelfRefresh Entry Idle H L X X X X L L L H SelfRefresh Exit Idle
H X X X
(SelfRefresh)
L H X X X
X
L H H H Clock Suspend Mode Entry Active H L X X X X X X X X Power Down Mode Entry Any (5) H X X X
H L X X X
X
ed2k怎么下载L H H H Clock Suspend Mode Exit Active L H X X X X X X X X Power Down Mode Exit Any L H X X X交通标志标牌
X H X X X
(PowerDown)
L H H H
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Data Write/Output Enable Active H X L X X
X X X X X
Data Mask/Output Disable
Active H X H X X X X X X X
Note: 1. V=Valid X=Don't Care L=Low level H=High level
2. CKE n signal is input level when commands are provided.
CKE n-1 signal is input level one clock cycle before the commands are provided. 3. The are states of bank designated by BS signal. 4. Device state is 1, 2, 4, 8, and full page burst operation. 5. Power Down Mode can not enter in the burst operation.
When this command is asrted in the burst cycle, device state is clock suspend mode.
