EtronTech
EM6AA160TSA
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc. rerves the right to change products or specification without notice.
16M x 16 bit DDR Synchronous DRAM (SDRAM)
Etron Confidential Preliminary (Rev. 1.2 May. / 2009)
Features
• Fast clock rate: 250/200MHz • Differential Clock CK & CK • Bi-directional DQS
• DLL enable/disable by EMRS • Fully synchronous operation • Internal pipeline architecture叶德娴
• Four internal banks, 4M x 16-bit for each bank
• Programmable Mode and Extended Mode registers - CAS Latency: 2.5, 3 - Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved • Individual byte write mask control • DM Write Latency = 0
• Auto Refresh and Self Refresh • 8192 refresh cycles / 64ms
• Precharge & active power down
• Power supplies: V DD & V DDQ = 2.5V ± 5% • Interface: SSTL_2 I/O Interface
• Package: 66 Pin TSOP II, 0.65mm pin pitch - Pb free and Halogen free
Overview
The EM6AA160 SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 256 Mbits. It is internally configured as a quad 4M x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK .d Read and write access to the SDRAM are burst oriented; access start at a lected location and continue for a programmed number of locations in a programmed quence. Access begin with the registration of a BankActivate command which is then followed by a Read o
r Write command. The EM6AA160 provides programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be enabled to provide a lf-timed row precharge that is initiated at the end of the burst quence. The refresh functions, either Auto or Self Refresh are easy to u. In addition, EM6AA160 features programmable DLL option. By having a programmable mode register and extended mode register, the system can choo the most suitable modes to maximize its performance. The devices are well suited for applications requiring high memory bandwidth, result in a device particularly well suited to high performance main memory and graphics applications.
Table 1.Ordering Information
Part Number
Clock
Frequency
Data Rate Package
EM6AA160TSA-4G 250MHz 500Mbps/pin TSOPII EM6AA160TSA-5G 200MHz 400Mbps/pin TSOPII TS: indicates TSOP II package
云南白药药膏
G : indicates Pb free and Halogen free
A: indicates Generation Code
Figure 1. Pin Assignment (Top View)
VSSQ 166VDD VSS 265DQ0DQ15364VDDQ VSSQ 463DQ1DQ14562DQ2DQ13661VSSQ VDDQ 760DQ3DQ12859DQ4DQ11958VDDQ VSSQ 1057DQ5DQ101156DQ6DQ91255VSSQ VDDQ 1354DQ7DQ81453NC NC 1552VDDQ 1651LDQS UDQS 1849VDD VREF 1948NC VSS 2047LDM UDM 2245CAS CK 2344RAS CKE 2443CS NC 2542NC A122641BA0A112740BA1A92839A10/AP
A82938A0A71750NC NC 2146WE CK 3136A2A53235A3A433饭桌
34
VDD
VSS
3037A1A6
Figure 2. Block Diagram
CK
CKE
CS RAS CAS WE
A10/AP
组织生活会议程A9~
A0CK
蒜苗炒腊肉Pin Descriptions
Table 2. Pin Details of EM6AA160
V DD Supply Power Supply: 2.5V 5% .
V SS Supply Ground
V DDQ Supply DQ Power: 2.5V 5%. Provide isolated power to DQs for improved noi immunity. V SSQ Supply DQ Ground: Provide isolated ground to DQs for improved noi immunity.
V REF Supply Reference Voltage for Inputs: +0.5*V DDQ
NC -
No Connect: The pins should be left unconnected.
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 3 shows the truth table for the operation commands.
Table 3. Truth Table (Note (1), (2))
2. CKE n signal is input level when commands are provided.
CKE n-1 signal is input level one clock cycle before the commands are provided.
3. The are states of bank designated by BA signal.穿拖鞋开车
4. Device state is 2, 4, and 8 burst operation.
5. LDM and UDM can be enabled respectively.
Mode Register Set (MRS)
The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs CAS Latency, Burst Type, and Burst Length to make the DDR SDRAM uful for a variety of applications. The default value of the Mode Register is not defined; therefore the Mode Register must be written by the ur. Values stored in the register will be retained until the register is reprogrammed. The Mode Register is written by asrting Low on CS, RAS, CAS, WE, BA1 and BA0 (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and CKE should be High). The state of address pins A0~A12 and BA0, BA1 in the same cycle in which CS, RAS, CAS and WE are asrted Low is written into the Mode Register. A minimu
m of two clock cycles, tMRD, are required to complete the write operation in the Mode Register. The Mode Register is divided into various fields depending on functionality. The Burst Length us A0~A2, Burst Type us A3, and CAS Latency (read latency from column address) us A4~A6. A logic 0 should be programmed to all the undefined address to ensure future compatibility. Rerved states should not be ud to avoid unknown device operation or incompatibility with future versions. Refer to the table for specific codes for various burst lengths, burst types and CAS latencies.
剪纸的历史和由来Table 4. Mode Register Bitmap
Field •Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and lects the Burst Length to be 2, 4, 8.
Table 5. Burst Length
Length A2 A1 A0 Burst
0 0 0 Rerved
0 0 1 2
0 1 0 4
氢溴酸右美沙芬片的作用0 1 1 8
1 0 0 Rerved
1 0 1 Rerved
1 1 0 Rerved
1 1 1 Rerved
