SY56011R
芋圆做法Low Voltage 1.2V/1.8V/2.5V CML 1:2 Fanout Buffer 6.4Gbps with Equalization
Preliminary
Precision Edge is a registered trademark of Micrel, Inc.
QFN and Micro LeadFrame are registered trademarks of Amkor Technology.
Micrel Inc. • 2180 Fortune Drive • San Jo, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
General Description
The SY56011R is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:2 Fanout Buffer with input equalization. The SY56011R can process clock signals as fast as 4.5 GHz or data patterns up to 6.4Gbps.
The differential input includes Micrel’s unique, 3-pin input termination architecture that interfaces to CM
depaulL differential signals, without any level-shifting or termination resistor networks in the signal path. The differential input can also accept AC-coupled LVPECL and LVDS signals. Input voltages as small as 200mV (400mV pp ) are applied before the 9”, 18” or 27” FR4 transmission line. For AC-coupled input interface applications, an internal voltage reference is provided to bias the V T pin. The outputs are CML, with extremely fast ri/fall times guaranteed to be less than 80ps.
The SY56011R operates from a 2.5V ±5% core supply and a 1.2V, 1.8V or 2.5V ±5% output supply and is guaranteed over the full industrial temperature range (–40°C to +85°C). The SY56011R is part of Micrel’s
high-speed, Precision Edge ®
product line.
Datasheets and support documentation can be found on Micrel’s web site at: .
Functional Block Diagram
Precision Edge ®
Features
• 1.2V/1.8V/2.5V CML 1:2 Fanout Buffer • Equalizes 9, 18, 27 inches of FR4
• Guaranteed AC performance over temperature and voltage:
– DC-to > 6.4Gbps Data throughput – DC-to > 4.5GHz Clock throughput – <280ps propagation delay (IN-to-Q) – <15ps within-device skew – <80ps ri/fall times • Ultra-low jitter design – <1ps R
MS random jitter • High-speed CML outputs
• 2.5V ±5% V CC , 1.2/1.8V/2.5V ±5% V CCO power supply operation
• Industrial temperature range: –40°C to +85°C • Available in 16-pin (3mm x 3mm) QFN package
Applications
• Data Distribution:
• SONET clock and data distribution
• Fiber Channel clock and data distribution •
Gigabit Ethernet clock and data distribution
Markets
•
Storage • ATE
• Test and measurement
豪车排行榜• Enterpri networking equipment • High-end rvers
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Metro area network equipment
Ordering Information(1)
Notes:
1. Contact factory for die availability. Dice are guaranteed at T A = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
16-Pin QFN
Truth Table
Pin Description
Absolute Maximum Ratings(1)
工作宣言Supply Voltage (V CC) ............................... –0.5V to +3.0V Supply Voltage (V CCO) ............................. –0.5V to +3.0V V CC - V CCO ............................................................... <1.8V V CCO - V CC ............................................................... <0.5V Input Voltage (V IN) ....................................... –0.5V to V CC CML Output Voltage (V OUT) ......................... 0.6V to 3.0V Current (V T)
Source or sink on VT pin ............................. ±100mA Input Current
Source or sink Current on (IN, /IN) ................ ±50mA Maximum operating Junction Temperature .......... 125°C Lead Temperature (soldering, 20c.) .................. 260°C Storage Temperature (T s) .................... –65°C to +150°C
Operating Ratings(2)
Supply Voltage (V CC) .......................... 2.375V to 2.625V (V CCO) .......................... 1.14V to 2.625V Ambient Temperature (T A) ................... –40°C to +85°C Package Thermal Resistance(3)
QFN
Still-air (θJA) .................................................. 75°C/W Junction-to-board (ψJB) ................................ 33°C/W
DC Electrical Characteristics(4)
T
= –40°C to +85°C, unless otherwi stated.
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than tho detailed in the operational ctions of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes expod pad is soldered (or equivalent) to the device's most negative potential on the PCB. ψJB and θJA
values are determined for a 4-layer board in still-air number, unless otherwi stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.金的故事
5. V IH(max) is specified when V T is floating.我在唯品会工作了四年
CML Outputs DC Electrical Characteristics(6)
V CCO = 1.14V to 1.26V R L = 50Ω to V CCO,
V CCO = 1.7V to 1.9V, 2.375V to 2.625V, R L = 50Ω to V CCO or 100Ω across the outputs.
V CC = 2.375V to 2.625V; T A = –40°C to +85°C, unless otherwi stated.
Three Level EQ Input DC Electrical Characteristics(6)
V
= 2.375V to 2.625V; T = –40°C to +85°C, unless otherwi stated.
金石之学
6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
AC Electrical Characteristics
V CCO = 1.14V to 1.26V R L = 50Ω to V CCO,
V CCO = 1.7V to 1.9V, 2.375V to 2.625V, R L = 50Ω to V CCO or 100Ω across the outputs,
V CC = 2.375V to 2.625V; T A = –40°C to +85°C, unless otherwi stated.
Notes:
7. Propagation delay is measured with no attenuating transmission line connected to the input.
8. Within-device skew is measured across all outputs under identical input transition, temperature and power supply.
9. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
10. Random jitter is measured with a K28.7 pattern, measured at ≤ f MAX.
July 2008 6 M9999-070208-A
or (408) 955-1690
