SY58606U
4.25Gbps Precision, 1:2 CML Fanout Buffer
with Internal Termination and Fail Safe Input Precision Edge is a registered trademark of Micrel, Inc.
General Description
The SY58606U is a 2.5/3.3V, high-speed, fully
differential 1:2 CML fanout buffer optimized to provide
two identical output copies with less than 15ps of skew
and only 146fs RMS of pha jitter. The SY58606U can
process clock signals as fast as 3GHz or data patterns
up to 4.25Gbps.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC- or DC-coupled)
as small as 100mV (200mV pp) without any level-shifting
or termination resistor networks in the signal path. For
AC-coupled input interface applications, an integrated
voltage reference (V REF-AC) is provided to bias the V T pin.
The outputs are 400mV CML, with extremely fast
ri/fall times guaranteed to be less than 85ps.
The SY58606U operates from a 2.5V ±5% supply or
3.3V ±10% supply and is guaranteed over the full
industrial temperature range (–40°C to +85°C). For
applications that require LVPECL or LVDS outputs,
consider Micrel’s SY58607U and SY58608U, 1:2 fanout
buffers with 800mV and 325mV output swings
respectively. The SY58606U is part of Micrel’s high-
speed, Precision Edge® product line.
Datasheets and support documentation can be found on
Micrel’s web site at:
Functional Block Diagram
Precision Edge®
Features
•Precision 1:2, 400mV CML fanout buffer
•Ultra-low jitter design
– 146fs RMS pha jitter (typ)
•Guaranteed AC performance over temperature and
voltage:
– DC-to > 4.25Gbps throughput
– <320ps propagation delay (IN-to-Q)
– <15ps within-device skew
– <85ps ri/fall times
•Fail Safe Input
– Prevents outputs from oscillating when input is
invalid
•High-speed CML outputs
•2.5V ±5% or 3.3V ±10% power supply operation
•Industrial temperature range: –40°C to +85°C
•Available in 16-pin (3mm x 3mm) QFN package
塑胸Applications
•Data Distribution: OC-48, OC-48+FEC, XAUI
•SONET clock and data distribution
•Fibre Channel clock and data distribution
•Gigabit Ethernet clock and data distribution
Markets
• Storage
• ATE
•Test and measurement
曲折的拼音•Enterpri networking equipment
七夕音乐
• High-end rvers
• Access
•Metro area network equipment
November 2011 2 M9999-110411-D
Ordering Information (1)
Part Number
Package Type
Operating Range
Package Marking SY58606UMG QFN-16 Pb-Free
Industrial
淘宝网首页男装606U with Pb-Free
bar-line indicator SY58606UMGTR (2) QFN-16 Pb-Free
Industrial
606U with Pb-Free bar-line indicator
Notes: 1.
Contact factory for die availability. Dice are guaranteed at T A = 25°C, DC Electricals only. All devices are Pb-Free. 2. Tape and Reel.
Pin Configuration
16-Pin QFN
Pin Description
Pin Number
Pin Name Pin Function
1, 4
IN, /IN
Differential Input: This input pair is the differential signal input to the device. Input
accepts DC-coupled differential signals as small as 100mV (200mV PP ). Each pin of this pair internally terminates with 50Ω to the VT pin. If the input swing falls below a certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. See “Input Interface Applications” subction.
2 VT
Input Termination Center-Tap: Each side of the differential input pair terminates to VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” subction. 3 VREF-AC
Reference Voltage: This output bias to V CC –1.2V. It is ud for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01µF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA. See “Input Interface Applications” subction. 5, 8,13, 16 VCC Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as clo to the V CC pins as possible.
6, 7, 14, 15 GND, Expod pad Ground: Expod pad must be connected to a ground plane that is the same potential as the ground pins.
9, 10 11, 12
/Q1, Q1 /Q0, Q0
CML Differential Output Pairs: Differential buffered copies of the input signal. The output swing is typi
cally 400mV. Unud output pair may be left floating with no impact on jitter. See “CML Output Termination” subction.
Absolute Maximum Ratings(1)
Supply Voltage (V CC)...............................–0.5V to +4.0V Input Voltage (V IN).......................................–0.5V to V CC CML Output Voltage (V OUT)..........V CC-1.0V to V CC+0.5V Current (V T)
Source or sink on ±100mA Input Current
Source or sink Current on (IN, /IN)................±50mA Current (V REF)
Source or sink current on V REF-AC(4)..............±1.5mA Maximum operating 125°C Lead Temperature (soldering, 20c.)..................260°C Storage Temperature (T s)....................–65°C to +150°C Operating Ratings(2)
Supply Voltage (V IN)........................+2.375V to +3.60V Ambient Temperature (T A)...................–40°C to +85°C Package Thermal Resistance(3)
QFN
Still-air (θJA)............................................60°C/W
Junction-to-board (ψJB).........................33°C/W
DC Electrical Characteristics(5)
T A = –40°C to +85°C, unless otherwi stated.
西游记33回概括Symbol Parameter Condition Min Typ Max Units
V CC Power Supply Voltage Range 2.375
3.0 2.5
3.3
2.625
3.6
V
I CC Power Supply Current No load, max. V CC60
77
mA R DIFF_IN Differential Input Resistance
(IN-to-/IN) 90 100 110 Ω
V IH Input HIGH Voltage
(IN, /IN) IN, /IN, Note 7
V CC–1.6 V CC V
V IL Input LOW Voltage
(IN, /IN) IN, /IN
V IH–0.1 V
V IN Input Voltage Swing
(IN, /IN) e Figure 3a, Note 6
0.1 1.7 V
V DIFF_IN Differential Input Voltage Swing
(|IN - /IN|) e Figure 3b
0.2 V
V IN_FSI Input Voltage Threshold that
Triggers FSI 30 100
mV V REF-AC Output Reference Voltage V CC–1.3 V CC–1.2 V CC–1.1 V
V T_IN Voltage from Input to V T 1.28
V Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than tho detailed in the operational ctions of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes expod pad is soldered (or equivalent) to the device's most negative potential on the PCB. ψJB and θJA
values are determined for a 4-layer board in still-air number, unless otherwi stated.
4. Due to the limited drive capability, u for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V IN (max) is specified when V T is floating.雾霾作文
7. V IH (min) not lower than 1.2V.
November 2011 3 M9999-110411-D
CML Outputs DC Electrical Characteristics (7)
V CC = +2.5V ±5% or +3.3V ±10%, R L = 100Ω across the outputs; T A = –40°C to +85°C, unless otherwi stated.
Symbol Parameter Condition Min Typ Max Units V OH Output HIGH Voltage R L = 50Ω to V CC V CC -0.020 V CC -0.010 V CC V V OUT Output Voltage Swing
See Figure 3a 325 400
mV
V DIFF_OUT
Differential Output Voltage Swing
See Figure 3b
650 800 mV
R OUT Output Source Impedance
45
50 55 Ω
怎么戴假发Note:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
AC Electrical Characteristics
V CC = +2.5V ±5% or +3.3V ±10%, R L = 100Ω across the outputs, Input t r/t f: <300ps; T A = –40°C to +85°C, unless otherwi stated.
Symbol Parameter Condition Min Typ Max Units
NRZ Data 4.25 Gbps
f MAX Maximum
Frequency
V OUT > 200mV Clock 2.5 3.0 GHz
V IN: 100mV-200mV 150 270 400 ps
t PD Propagation Delay IN-to-Q
V IN:
200mV-800mV 120 220 320 ps Within Device Skew Note 8 3 15 ps
t Skew
Part-to-Part Skew Note 9 100 ps
t Jitter RMS Pha Jitter Output = 622MHz
Integration Range: 12kHz – 20MHz 146 fs
t R t F Output Ri/Fall Times
(20% to 80%) At full output swing.
30 50 85 ps
Duty Cycle Differential I/O 47 53 % Notes:
8. Within device skew is measured between two different outputs under identical input transitions.
9. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
凌云的意思respective inputs.
Pha Noi Plot
