FPGA片上资源-FDR/FDRE/FDRS/FDRSE
2010-11-23 17:47
FDR : D Flip-Flop with Synchronous Ret
/itp/xilinx5/data/docs/lib/lib0170_154.html
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Primitive | Primitive | Primitive | Primitive中国最长的电视剧 | 母子情爱Macro 虚物 | Macro | FDR is a single D-type flip-flop with data (D) and synchronous ret (R) inputs and data output (Q). The synchronous ret (R) input, when High, overrides all other inputs and rets the Q output Low on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low during the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. Macro |
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FDR is a single D-type flip-flop with data (D) and synchronous ret (R) inputs and data output (Q). The synchronous ret (R) input, when High, overrides all other inputs and rets the Q output Low on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low during the Low-to-High clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
VHDL Inference Code
architecture Behavioral of fdr is
begin
process (C) begin
if (C' event and C = '1') then
if (R = '1') then
Q <= '0';
el
Q <= D;
end if;
end if;
end process;
end Behavioral;
Verilog Inference Code
always @ (podge C) begin
if (R)
Q <= 0;
el
Q <= D;
end
FDRE : D Flip-Flop with Clock Enable and Synchronous Ret
/itp/xilinx5/data/docs/lib/lib0172_156.html
FDRE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous ret (R) inputs and data output (Q). The synchronous ret (R) input, when High, overrides all other inputs and rets the Q output Low on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low and CE is High during the Low-to-High clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
VHDL Inference Code
architecture Behavioral of fdre is
begin
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process (C) begin
if (C’ event and C = ’1’) then
八字命理if (R = ’1’) then
Q <= ’0’;
elsif (CE = ’1’) then
Q <= D;
end if;
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end if;
end process;
end Behavioral;
Verilog Inference Code
always @ (podge C) begin
if (R)
Q <= 0;
el if (CE)
Q <= D;
end
FDRS : D Flip-Flop with Synchronous Ret and Set
/itp/xilinx5/data/docs/lib/lib0174_158.html
FDRS is a single D-type flip-flop with data (D), synchronous t (S), and synchronous ret (R) inputs and data output (Q). The synchronous ret (R) input, when High, overrides all other inputs and rets the Q output Low during the Low-to-High clock (C) tr
ansition. (Ret has precedence over Set.) When S is High and R is Low, the flip-flop is t, output High, during the Low-to-High clock transition. When R and S are Low, data on the (D) input is loaded into the flip-flop during the Low-to-High clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
VHDL Inference Code
architecture Behavioral of fdrs is
begin
process (C) begin
if (C' event and C = '1') then
if (R = '1') then
Q <= '0';
elsif (S = '1') then
Q <= '1';
el
Q <= D;
end if;
end if;
end process;
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Verilog Inference Code
always @ (podge C) begin
if (R)
Q <= 0;
el if (S)
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el
Q <= D;
end
FDRSE : D Flip-Flop with Synchronous Ret and Set and Clock Enable
/itp/xilinx5/data/docs/lib/lib0176_160.html
FDRSE is a single D-type flip-flop with synchronous ret (R), synchronous t (S), and clock enable (CE) inputs and data output (Q). The ret (R) input, when High, overrides all other inputs and rets the Q output Low during the Low-to-High clock transition. (Ret has precedence over Set.) When the t (S) input is High and R is Low, the flip-flop is t, output High, during the Low-to-High clock (C) transition. Data on the D input is loaded into the flip-flop when R and S are Low and CE is High during the Low-to-High clock transition.
