专利名称：Method and system for hardware蛋兜
accelerated verification of digital circuit
design and its testbench
阴茎按摩
发明人：Jyotirmoy Daw,Sanjay Gupta,Suresh
Krishnamurthy
申请号：US10972361
申请日：20041026
公开号：US07257802B2
公开日：
上校的涩涩小妻>辅导员职责20070814
专利内容由知识产权出版社提供
铁路工作专利附图：点燃的蜡烛
摘要：A system and method is prented for synthesizing both a design under test
(DUT) and its test environment (i.e., the testbench for the DUT), into an equivalent structural model suitable for execution on a reconfigurable hardware platform. This may be achieved without any change in the existing verification methodology. Behavioral HDL may be translated into a form that can be executed on a reconfigurable hardware platform. A t of compilation transforms are provided that convert behavioral constructs into RTL constructs that can be directly mapped onto an emulator. Such transforms are provided by introducing the concepts of a behavioral clock and a time advance finite state machine (FSM) that determines simulation time and quences concurrent computing blocks in the DUT and the testbench.什么地工作
申请人：Jyotirmoy Daw,Sanjay Gupta,Suresh Krishnamurthy
地址：Noida IN,Noida IN,Noida IN
国籍：IN,IN,IN
代理机构：Banner & Witcoff, Ltd.
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