SPI GPIO Expander
December 2010
Reference Design RD1073
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Introduction
Microprocessors often have a limited number of general purpo I/O (GPIO) ports. This approach helps reduce pin count and shrink package size. I/O expanders, or port expanders, provide I/O expansion capabilities for micropro-cessors. They allow designers to save the GPIO ports on the microprocessor for other critical tasks. There are many generic I/O expander devices available. Most of them u low pin count protocols, such as I 2C or SPI, as the interface to the host. This design provides a programmable solution for rial expansion of GPIOs. It us a Serial Peripheral Interface (SPI) as the interface between the microprocessor and the GPIOs. The design provides addi-tional control and monitoring capabilities for the microprocessor when it does not have sufficient GPIOs to do the job.
Features
•SPI-compatible rial interface to the host •16 GPIOs can be configured as inputs or outputs
•GPIOs configured as inputs can cau an interrupt request to the host •Interrupts can be masked if necessary
•All GPIOs are configured as inputs at hardware ret
•16 GPIOs can be accesd individually at once; some combinations of four or eight GPIOs can be accesd as a group; all 16 GPIOs can be accesd as a group.
Interface
Figure 1. SPI to GPIO Interface
Functional Description
This design provides up to 16 ports, P0 to P15, controlled through the SPI-compatible rial interface. Each port is individually ur-configurable as either a logic input or a logic output. A power-on ret or ret signal initializes the 16 ports as inputs. This design consists of a no-op register, a 16-bit configuration register, a 16-bit mask register, a 16-bit input register and a 16-bit output register. The 24-bit shift register controls the rial-in and rial-out of the data to and from the host. The interrupt generation block generates an interrupt signal to the host when one of the input ports changes its logic state. Figure
2 is the functional block diagram.
Figure 2. Functional Block Diagram
Table 1. SPI GPIO Expander I/O Interface Descriptions
Communication with the Host
This design communicates with the host through the SPI-compatible 4-wire rial interface. DIN is sa
mpled on the rising edge of SCLK when the CSn pin is low. DOUT provides a copy of the data that was received 23.5 clocks ear-lier at the DIN pin or outputs internal register data upon request when CSn is low. When CSn is high, this design ignores all activity on SCLK and DIN. DOUT must be high impedance when CSn is high.
Data Format from the Host
Between taking the CSn pin low and taking it back high, the host should clock at least 24 bits into DIN. Only the last 24 bits will be retained. Bit D23 is the first in and bit D0 is the last in. Bit D23 is a command bit. Its logic 0 indicates a WRITE from the host to a register and logic 1 indicates a READ from a register by the host. Bits D22-D16 are defined as the address bits. The address bits indicate the address of the register that the host plans to access in this operation. Bits D15-D0 are the data bits the host writes to the register which is lected by the address bits.
Signal Name Direction
Active State
Definition
Host Interface
SCLK Input N/A 4-wire interface rial clock input port.CSn Input Low 4-wire interface chip-lect input, active low.DIN Input N/A 4-wire interface rial data input port.DOUT Output Low, High, HiZ
4-wire interface rial data output port.RST Input High CPLD rest signal.
INTn
Output
Low
生活还得继续
Interrupt signal to the host, becomes active when one of the input GPIOs changes state.
Back End Interface
P0 to P15度文尼
Output, Input
Low, High, HiZ
GPIO Ports 0 to 15.
Register Definitions
Registers in this design include a no-op register, a 16-bit configuration register, a 16-bit mask register, a 16-bit out-put register and a 16-bit input register.
The no-op register indicates no operation. This register can only be written by the host and its address is 0x00.Writing to this register does not change other register states or port states but will shift out the data in the D15 to D0 positions of the shift register.
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The configuration register is ud to configure the directions of the ports. This is a 16-bit register where each bit corresponds to a port. Bit 0 corresponds to P0, bit 1 corresponds to P1, etc. Setting the bit in the respective config-ure register enables the corresponding port as an input. In the same way, clearing the bit in the configuration regis-ter enables the corresponding port as an output.Table 2. Configuration Register Definitions
The mask register is ud to mask the interrupt. This is a 16-bit wide register and each bit corresponds to a port.Bit 0 corresponds to P0, bit 1 corresponds to P1, etc. Setting the bit in the mas
k register will mask the interrupt gen-eration of a specific port. Clearing the bit in the mask register enables the interrupt generation from that port.Table 3. Mask Register Definitions
The output register is a write-only register. It ts the logic levels of the output ports defined by the configuration register. This is a 16-bit register and each bit corresponds to a port. Several addressing methods for output regis-ters are available. As shown in Table 4, any port can be read individually. Some combinations of four or eight ports can be read simultaneously. All 16 ports can be read together. Register Address Width Access Ret Value Bit Definition
Configuration register
0x01
16
R/W
0xffff
‘1’ configures the port as an input;‘0’ configures the port as an output.
Register Address Width Access Ret Value Bit Definition
Mask register
0x02
16
R/W
0xffff
‘1’ masks interrupt generation;‘0’ enables interrupt generation.
Table 4. Output Register Address Map Definitions
Register
Access Address Ret Value
Output register port 0
(Data bit D0. Data bits D1-D15 are ignored).W 0x030x1Output register port 1
(Data bit D1. Data bits D0 and D1-D15 are ignored).W 0x040x1Output register port 2
(Data bit D2. Data bits D0-D1 and D3-D15 are ignored).W 0x050x1Output register port 3
(Data bit D3. Data bits D0-D2 and D4-D15 are ignored).W 0x060x1Output register port 4
sata模式选择(Data bit D4. Data bits D0-D3 and D5-D15 are ignored).W 0x070x1Output register port 5
(Data bit D5. Data bits D0-D4 and D6-D15 are ignored).W 0x080x1Output register port 6
(Data bit D6. Data bits D0-D5 and D7-D15 are ignored).W 0x090x1Output register port 7
叶圣陶童话集(Data bit D7. Data bits D0-D6 and D8-D15 are ignored).
W
0x0A
0x1
The input register is a read-only register. It reflects the incoming logic levels of the ports, regardless of whether the port is defined as an input or an output. This is a 16-bit register and each bit corresponds to a port. As with the out-put register, veral addressing methods are available for input registers. Any port can be read individually. Some combinations of four or eight ports can be read simultaneously. All 16 ports can be read together. Table 5 shows the input register addressing methods.
Output register port 8
(Data bit D8. Data bits D0-D7 and D9-D15 are ignored).W 0x0B 0x1Output register port 9
(Data bit D9. Data bits D0-D8 and D10-D15 are ignored).W 0x0C 0x1Output register port 10
(Data bit D10. Data bits D0-D9 and D11-D15 are ignored).W 0x0D 0x1Output register port 11
(Data bit D11. Data bits D0-D10 and D12-D15 are ignored).W 0x0E 0x1Output register port 12
(Data bit D12. Data bits D0-D11 and D13-D15 are ignored).W 0x0F 0x1Output register port 13
(Data bit D13. Data bits D0-D12 and D14-D15 are ignored).W 0x100x1Output register port 14
(Data bit D14. Data bits D0-D13 and D15 are ignored).W 0x110x1Output register port 15
(Data bit D15. Data bits D0-D14 are ignored).W 0x120x1Output register ports 0-3
(Data bits D0-D3. Data bits D4-D15 are ignored).
W 0x130xf Output register ports 4-7
(Data bits D4-D7. Data bits D0-D3 and D8-D15 are ignored).W 0x140xf Output register ports 8-11
(Data bits D8-D11. Data bits D0-D7 and D12-D15 are ignored).W 0x150xf Output register ports 12-15
(Data bits D12-D15. Data bits D0-D11 are ignored).W 0x160xf Output register ports 0-7
(Data bits D0-D7. Data bits D8-D15 are ignored).W 0x170xff Output register ports 8-15
(Data bits D8-D15. Data bits D0-D7 are ignored).W 0x180xff Output register ports 0-15.
W
0x19
0xffff
Table 5. Definition of Input Register Addressing Map
Register
Access Address Ret Value
Input register port 0
(Data bit D0. Data bits D1-D15 are not changed).
R 0x030x0Input register port 1
(Data bit D1. Data bit D0 and data bits D1-D15 are not changed).R 0x040x0Input register port 2
(Data bit D2. Data bits D0-D1 and D3-D15 are not changed).R 0x050x0Input register port 3
(Data bit D3. Data bits D0-D2 and D4-D15 are not changed).R 0x060x0Input register port 4
(Data bit D4. Data bits D0-D3 and D5-D15 are not changed).R 0x070x0Input register port 5
(Data bit D5. Data bits D0-D4 and D6-D15 are not changed).
R
0x08
0x0
Table 4. Output Register Address Map Definitions (Continued)
Register
Access Address Ret Value
Host Writing to Registers
The no-op register, configuration register, mask register and output register can be written by the host. When CSn is low, it shifts in the DIN data on the rising edge of SCLK. When CSn goes high, the 24 bits in the shift register are then decoded and executed.
U the following quence for the host to write to a register:
1.Take SCLK low.
2.Take CSn low.
3.Clock 24 bits of data into the DIN with D23 first and D0 last (bit D23 is low, indicating the host is writing to the register; bits D22-D16 indicate the register address; bits D15 to D0 are the data written to the register).
4.Take SCLK low.
5.Take CSn high.
Figure 3 shows the relative timing of a WRITE from the host.
Input register port 6
(Data bit D6. Data bits D0-D5 and D7-D15 are not changed).R 0x090x0Input register port 7
(Data bit D7. Data bits D0-D6 and D8-D15 are not changed).R 0x0A 0x0Input register port 8建树是什么意思
(Data bit D8. Data bits D0-D7 and D9-D15 are not changed).R 0x0B 0x0Input register port 9
(Data bit D9. Data bits D0-D8 and D10-D15 are not changed).R 0x0C 0x0Input register port 10
晚婚晚育假(Data bit D10. Data bits D0-D9 and D11-D15 are not changed).R 0x0D 0x0Input register port 11
(Data bit D11. Data bits D0-D10 and D12-D15 are not changed).R 0x0E 0x0Input register port 12
(Data bit D12. Data bits D0-D11 and D13-D15 are not changed).R 0x0F 0x0Input register port 13
摘抄名言名句(Data bit D13. Data bits D0-D12 and D14-D15 are not changed).R 0x100x0Input register port 14
(Data bit D14. Data bits D0-D13 and D15 are not changed).R 0x110x0Input register port 15
(Data bit D15. Data bits D0-D14 are not changed).R 0x120x0Input register ports 0-3
(Data bits D0-D3. Data bits D4-D15 are not changed).
R 0x130x0Input register ports 4-7
(Data bits D4-D7. Data bits D0-D3 and D8-D15 are not changed).R 0x140x0Input register ports 8-11
(Data bits D8-D11. Data bits D0-D7 and D12-D15 are not changed).R 0x150x0Input register ports 12-15
(Data bits D12-D15. Data bits D0-D11 are not changed).R 0x160x0Input register ports 0-7
(Data bits D0-D7. Data bits D8-D15 are not changed).R 0x170x00Input register ports 8-15
(Data bits D8-D15. Data bits D0-D7 are not changed).R 0x180x00Input register ports 0-15
R
0x19
0x0000
Table 5. Definition of Input Register Addressing Map (Continued)
Register
Access Address Ret Value
