/
IN-1
HOME CONTENTS
INDEX Index
Symbols
$display 2-12
** (power operator)B-44
+: (variable part-lect operator)B-38-: (variable part-lect operator)B-38<<< (arithmetic shift operator)B-45>>> (arithmetic shift operator)B-45”- ” operator 3-6,7-3”& ”operator 7-3
”+ ” operator 3-6,7-3”* ” operator 7-3”<” operator 3-6”>” operator 3-6‘define B-19‘el B-22‘elsif B-22‘
endif B-22
‘ifdef VERILOG_1995B-31,C-9‘ifdef VERILOG_2000B-31,C-9
‘ifdef, ‘el, ‘endif, ‘ifndef, and ‘elsif B-22‘ifndef B-22‘include B-20‘undef B-22
‘undefineall 2-4,C-10
A
adders 2-20,2-21
carry bit overflow 3-7
carry-lookahead adder A-11
hdlin_no_adder_feedthroughs 9-9hdlin_u_carry_in 9-14always block
edge expressions 2-30
always construct 1-22,2-4,2-26,3-37,6-1,6-6,8-29,B-14,B-16,C-7,D-4,D-5architectures in modules D-
5arithmetic shift operators B-45array access 2-31arrays of instances C-9Arrays of nets B-31,C-8assign 10-2assignments
always construct 1-22,2-4,2-26,3-37,6-1,
6-6,8-29,B-14,B-16,C-7,D-4,D-5blocking B-16,B-17
continuous 9-12,A-4,B-30,C-5initial B-5,B-6
nonblocking 1-22,B-16,B-17Asynchronous Designs 2-26asynchronous process 2-30
/
IN-2
HOME
CONTENTS INDEX B
backslash continuation of single-line
comments D-2behavioral code
including an embedded netlist 8-23binary numbers B-3bit access 3-31
bit and memory access 3-31bit-blasting B-23bit-truncation explicit 3-34bit-width
prefix for numbers B-3specifying in numbers B-3blocking and nonblocking B-16blocking assignments B-16,B-17bus_multiple_parator_style 8-20bus_naming_style variable 1-26bus_range_parator_style 8-20Busing B-23
C
carry-lookahead adder A-11ca statements cax,caz B-11
hdlin_check_ur_full_ca 9-5
hdlin_dont_infer_mux_for_resource_sharing
9-5
hdlin_infer_mux 9-7
hdlin_mux_size_limit 9-9in while loops 3-29
missing assignment in a ca statement
branch 3-29
SELECT_OP Inference 3-18ud in multiplexing logic 3-18warnings
full_ca applied to non-ca statements
9-5
cax B-11
caz B-11
casting operators B-37
coding guidelines for DC Ultra datapath
optimization bit-truncation implicit 3-34
combinational feedback loop 7-14
combinational logic 3-1
combinational while loop C-9
Comma-parated nsitivity lists B-31,C-9conditional assignments if-el A-21
conditional inclusion of code
‘ifdef,‘el,‘endif,‘ifndef,and ‘elsif Directives
B-22
constant propagation 2-19
continuous assignments 9-12,A-4,B-30,C-5hdlin_prohibit_nontri_multiple_drivers 9-12controlling signs B-37
蒜苗的做法
D
D flip-flop, e flip-flop
Data-Path Duplication A-16
dc_script_end directive 8-5,8-7,8-8decimal numbers B-3declaration requirements tri data type B-18Decoders 3-32decoders
for loop coding style 3-32
hdlin_share_all_operators 9-12indexing coding style 3-33defparam C-9
deprecated features 2-32
Design Compiler 1-16,1-25,1-26,2-26,3-7,4-18,5-3,8-19,8-25,8-26,C-6
differences between Presto Verilog and HDL
Compiler
inference reports
/
IN-3
HOME CONTENTS
INDEX D-6
integers D-4
latch inference improvement D-5MUX_OP inference D-5ops for a resource D-5resource declaration D-4syntax errors D-6three-states D-4
variables in named always block D-5directives ‘define B-19‘el B-22‘endif B-22‘include B-20‘undef B-22‘undefineall 2-4
dc_script_begin 8-5,8-7dc_script_end 8-5,8-7dont_infer_multibit 8-17full_ca 8-11
infer_multibit 8-16,8-17infer_mux 3-22
map_to_module 7-10one_cold 4-22,8-25one_hot 8-26
parallel_ca 8-27
parallel_ca ud with full_ca 8-12return_port_name 8-23
e also hdlin_ for variables simulation 2-31disable B-14
Display synthesis progress C-7divide operator C-9don’t care 3-29
don’t care inference
simulation versus synthesis 2-28don’t cares
in ca statements 3-29
simulation/synthesis mismatch 2-28dont_merge_with directive D-2
E
ELAB-2923-16ELAB-3024-17ELAB-3102-29ELAB-365D-4
ELAB-3666-10,D-4ELAB-900B-24embedded 3-29
embedding constaints and attributes dc_script_end 8-5,8-7
embedding constraints and attributes dc_script_begin 8-5,8-7enum directive 8-9
enumerated type inference report 5-11enumerated types 5-10,5-14
errors 2-12,3-22,6-2,6-10,7-11,8-6,8-8,8-15,8-27,9-7,9-12,B-7,B-23,B-25,D-4,D-5,D-6,D-7ELAB-3024-17ELAB-3666-10ELAB-900B-24
Explicit bit-truncation 3-34expression tree
optimized for delay 3-8
F
features not supported D-2feedback loop 7-14
feedback loops 9-8finite state machine 5-3automatic detection 5-1fsm_auto_inferring 5-3inference report 5-6log ssion 5-8
Finite State Machine Compiler D-2finite state machines
automatic detection 5-1flip 4-5
/
IN-4
HOME CONTENTS
INDEX flip-flop
asynchronous t and ret conditions for
flip-flops 9-6,9-8
clocked_on_also attribute 4-24control register inference
hdlin_ff_always_async_t_ret 9-6hdlin_ff_always_sync_t_ret 9-6D-flip-flop
D flip-flop with a synchronous load and an
asynchronous load 4-34
D flip-flop with an asynchronous ret 4-30D flip-flop with an asynchronous t 4-29D flip-flop with synchronous ret 4-33D flip-flop with synchronous t 4-32rising-edge-triggered D flip-flop 4-28feedback loops 9-8
hdlin_ff_always_async_t_ret 9-6,9-8hdlin_ff_always_sync_t_ret 9-6hdlin_report_inferred_modules 4-5infer as multibit 8-18inference report 4-5
master-slave latches 4-24SEQGENs 4-2
synchronous t and ret conditions for flip-flops 9-6
unmapped master-slave generic cell
(MSGEN)4-24
ud to describe the master-slave latch 4-24for loop 3-32,3-39,D-4Formality 5-14
咏雪名句
FSM verification 5-14fsm_auto_inferring 5-3full_ca 8-11
functional description
function declarations in 1-22
functions 1-25,2-31,2-32,2-34,5-2,6-2,7-11,8-6,8-8,8-22,8-23,8-29,B-5,B-20,B-33,C-6,GL-2我想和你一起起床
hdlin_infer_function_local_latches 2-35
G
gate-level constructs 1-22
H
hdlin_auto_full_ca 9-4
hdlin_auto_parallel_ca_early 9-5hdlin_black_box_pin_hdlc_style 9-5hdlin_build_lectop_for_var _index 9-5hdlin_check_ur_full_ca 9-5
hdlin_check_ur_parallel _ca 9-5hdlin_dont_check_param_width D-3
可以赚钱
hdlin_dont_infer_mux_ for_resource_sharing
9-5
hdlin_dont_infer_mux_for_resource_sharing
3-23
hdlin_enable_analysis_info D-3hdlin_enable_vpp C-10,D-3
hdlin_ff_always_async_t_ret 9-6,9-8hdlin_ff_always_async_t_ret directive 9-6hdlin_ff_always_sync_t_ret 9-6hdlin_hide_resource_line_numbers D-3hdlin_infer_block_local_latches 9-6hdlin_infer_enumerated_types 9-6hdlin_infer_function_local _latches 9-6hdlin_infer_mux 9-7
hdlin_keep_feedback 9-8hdlin_keep_inv_feedback D-3
hdlin_loop_invariant_code_motion 9-8hdlin_map_to_module 9-9hdlin_map_to_operator 9-9
hdlin_marge_nested_conditional_statements
自我价值感
D-3
hdlin_module_arch_name_split 9-9hdlin_mux_oversize_ratio 9-9hdlin_mux_size_limit 9-9hdlin_mux_size_min 9-9最小正整数
hdlin_no_adder_feedthroughs 9-9
/
IN-5
HOME
CONTENTS INDEX hdlin_no_quential_mapping 9-9hdlin_one_hot_one_cold_on 9-9
hdlin_optimize_array_references 9-10hdlin_optimize_ca_default 9-10
hdlin_optimize_enum_types 5-11,5-14,9-10hdlin_optimize_shift_expressions 9-10hdlin_optimize_slic
e_op 9-10hdlin_prerve_vpp D-3
hdlin_prerve_vpp_files D-3
hdlin_prohibit_nontri_multiple _drivers 9-12hdlin_prohibit_nontri_multiple_drivers 6-10hdlin_redundancy_elimination 9-12hdlin_reg_report_length D-3hdlin_report_fsm directive 5-3hdlin_report_mux_op 9-12hdlin_report_syn_cell 9-12hdlin_report_tri_state 9-12
hdlin_lector_simplify_effort 9-12hdlin_qmap_arch_depth 9-13hdlin_share_all_nodes 9-13
hdlin_share_all_operators 9-12,9-13hdlin_subprogram_default_values 9-14hdlin_translate_off_skip_text D-3hdlin_upca_names 9-14hdlin_u_carry_in 9-14hdlin_u_syn_shifter 9-14
hdlin_verbo_cell_naming 9-14hdlin_vpp_temporary_directory D-3hdlin_vrlg_std = 1995C-9hdlin_vrlg_std = 2000C-9
hdlin_warn_implicit_sign_conv 3-10hdlin_warn_implicit_wires 9-14hdlin_warn_ns_list 9-14
hdlin_while_loop_iterations 9-14hexadecimal numbers B-3hierarchical
boundaries 1-25constructs 1-22
I
If 4-5
if statements
hdlin_infer_mux 9-7in ca statements 3-29
In common subexpression elimination 7-17infer MUX_OP cells 3-22
ifdef VERILOG_1995B-31,C-9ifdef VERILOG_2001B-31,C-9if-el A-21
ignored functions 2-32ignored variables D-3Implementation D-10
implicit bit-truncation 3-34include B-20冬瓜蛤蜊汤
incompletely specified ca statement 3-30infer_multibit 8-16infer_mux 3-22
Inference reports 4-5inference reports
difference in Presto Verilog D-6enumerated types 5-11finite state machine 5-6multibit components 8-17Inferring Flip-Flops, e flip-flop initial assignment B-5,B-6inout
喜得孙子的祝福语connecting to gate B-18connecting to module B-18instances C-9
instantiations 1-22,1-25,1-26,2-6,2-8,2-9,2-10,6-9,10-2,10-3,B-18Integers D-4
L
label_applies_to directive D-2labels/hierarchical labels D-2latches
